OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/compiler: Rename brw_image_param to isl_image_param

Browse Source 
And move them to ISL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475>
This commit is contained in:
Caio Oliveira
2024-01-22 12:14:01 -08:00
parent 1314c5b357
commit a88084f8be
13 changed files with 104 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/compiler/nir/nir_intrinsics.py
View File

@@ -1950,7 +1950,7 @@ load("helper_arg_lo_agx", [], [], [CAN_ELIMINATE])
# dst[] = { Helper argument high 32 bits }.
load("helper_arg_hi_agx", [], [], [CAN_ELIMINATE])
# Intel-specific query for loading from the brw_image_param struct passed
# Intel-specific query for loading from the isl_image_param struct passed
# into the shader as a uniform. The variable is a deref to the image
# variable. The const index specifies which of the six parameters to load.
intrinsic("image_deref_load_param_intel", src_comp=[1], dest_comp=0,

26
src/gallium/drivers/crocus/crocus_program.c
View File

@@ -433,7 +433,7 @@ crocus_setup_uniforms(ASSERTED const struct intel_device_info *devinfo,
unsigned *out_num_cbufs)
{
const unsigned CROCUS_MAX_SYSTEM_VALUES =
PIPE_MAX_SHADER_IMAGES * BRW_IMAGE_PARAM_SIZE;
PIPE_MAX_SHADER_IMAGES * ISL_IMAGE_PARAM_SIZE;
enum brw_param_builtin *system_values =
rzalloc_array(mem_ctx, enum brw_param_builtin, CROCUS_MAX_SYSTEM_VALUES);
unsigned num_system_values = 0;
@@ -572,31 +572,31 @@ crocus_setup_uniforms(ASSERTED const struct intel_device_info *devinfo,
const unsigned img = var->data.binding + i;
img_idx[img] = num_system_values;
num_system_values += BRW_IMAGE_PARAM_SIZE;
num_system_values += ISL_IMAGE_PARAM_SIZE;
uint32_t *img_sv = &system_values[img_idx[img]];
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_OFFSET_OFFSET, img,
offsetof(struct brw_image_param, offset), 2);
img_sv + ISL_IMAGE_PARAM_OFFSET_OFFSET, img,
offsetof(struct isl_image_param, offset), 2);
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_SIZE_OFFSET, img,
offsetof(struct brw_image_param, size), 3);
img_sv + ISL_IMAGE_PARAM_SIZE_OFFSET, img,
offsetof(struct isl_image_param, size), 3);
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_STRIDE_OFFSET, img,
offsetof(struct brw_image_param, stride), 4);
img_sv + ISL_IMAGE_PARAM_STRIDE_OFFSET, img,
offsetof(struct isl_image_param, stride), 4);
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_TILING_OFFSET, img,
offsetof(struct brw_image_param, tiling), 3);
img_sv + ISL_IMAGE_PARAM_TILING_OFFSET, img,
offsetof(struct isl_image_param, tiling), 3);
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_SWIZZLING_OFFSET, img,
offsetof(struct brw_image_param, swizzling), 2);
img_sv + ISL_IMAGE_PARAM_SWIZZLING_OFFSET, img,
offsetof(struct isl_image_param, swizzling), 2);
}
}
b.cursor = nir_before_instr(instr);
offset = nir_iadd_imm(&b,
get_aoa_deref_offset(&b, deref, BRW_IMAGE_PARAM_SIZE * 4),
get_aoa_deref_offset(&b, deref, ISL_IMAGE_PARAM_SIZE * 4),
img_idx[var->data.binding] * 4 +
nir_intrinsic_base(intrin) * 16);
break;

14
src/gallium/drivers/crocus/crocus_state.c
View File

@@ -1430,7 +1430,7 @@ crocus_init_compute_context(struct crocus_batch *batch)
struct crocus_genx_state {
struct {
#if GFX_VER >= 7
struct brw_image_param image_param[PIPE_MAX_SHADER_IMAGES];
struct isl_image_param image_param[PIPE_MAX_SHADER_IMAGES];
#endif
} shaders[MESA_SHADER_STAGES];
@@ -3008,7 +3008,7 @@ crocus_create_surface(struct pipe_context *ctx,
#if GFX_VER >= 7
static void
fill_default_image_param(struct brw_image_param *param)
fill_default_image_param(struct isl_image_param *param)
{
memset(param, 0, sizeof(*param));
/* Set the swizzling shifts to all-ones to effectively disable swizzling --
@@ -3020,7 +3020,7 @@ fill_default_image_param(struct brw_image_param *param)
}
static void
fill_buffer_image_param(struct brw_image_param *param,
fill_buffer_image_param(struct isl_image_param *param,
enum pipe_format pfmt,
unsigned size)
{
@@ -3050,7 +3050,7 @@ crocus_set_shader_images(struct pipe_context *ctx,
gl_shader_stage stage = stage_from_pipe(p_stage);
struct crocus_shader_state *shs = &ice->state.shaders[stage];
struct crocus_genx_state *genx = ice->state.genx;
struct brw_image_param *image_params = genx->shaders[stage].image_param;
struct isl_image_param *image_params = genx->shaders[stage].image_param;
shs->bound_image_views &= ~u_bit_consecutive(start_slot, count);
@@ -3124,7 +3124,7 @@ crocus_set_shader_images(struct pipe_context *ctx,
stage == MESA_SHADER_COMPUTE ? CROCUS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
: CROCUS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
/* Broadwell also needs brw_image_params re-uploaded */
/* Broadwell also needs isl_image_params re-uploaded */
ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_CONSTANTS_VS << stage;
shs->sysvals_need_upload = true;
#endif
@@ -3551,10 +3551,10 @@ upload_sysvals(struct crocus_context *ice,
#if GFX_VER >= 7
unsigned img = BRW_PARAM_IMAGE_IDX(sysval);
unsigned offset = BRW_PARAM_IMAGE_OFFSET(sysval);
struct brw_image_param *param =
struct isl_image_param *param =
&genx->shaders[stage].image_param[img];
assert(offset < sizeof(struct brw_image_param));
assert(offset < sizeof(struct isl_image_param));
value = ((uint32_t *) param)[offset];
#endif
} else if (sysval == BRW_PARAM_BUILTIN_ZERO) {

26
src/gallium/drivers/iris/iris_program.c
View File

@@ -444,7 +444,7 @@ iris_setup_uniforms(ASSERTED const struct intel_device_info *devinfo,
unsigned system_values_start = ALIGN(kernel_input_size, sizeof(uint32_t));
const unsigned IRIS_MAX_SYSTEM_VALUES =
PIPE_MAX_SHADER_IMAGES * BRW_IMAGE_PARAM_SIZE;
PIPE_MAX_SHADER_IMAGES * ISL_IMAGE_PARAM_SIZE;
enum brw_param_builtin *system_values =
rzalloc_array(mem_ctx, enum brw_param_builtin, IRIS_MAX_SYSTEM_VALUES);
unsigned num_system_values = 0;
@@ -593,31 +593,31 @@ iris_setup_uniforms(ASSERTED const struct intel_device_info *devinfo,
const unsigned img = var->data.binding + i;
img_idx[img] = num_system_values;
num_system_values += BRW_IMAGE_PARAM_SIZE;
num_system_values += ISL_IMAGE_PARAM_SIZE;
uint32_t *img_sv = &system_values[img_idx[img]];
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_OFFSET_OFFSET, img,
offsetof(struct brw_image_param, offset), 2);
img_sv + ISL_IMAGE_PARAM_OFFSET_OFFSET, img,
offsetof(struct isl_image_param, offset), 2);
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_SIZE_OFFSET, img,
offsetof(struct brw_image_param, size), 3);
img_sv + ISL_IMAGE_PARAM_SIZE_OFFSET, img,
offsetof(struct isl_image_param, size), 3);
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_STRIDE_OFFSET, img,
offsetof(struct brw_image_param, stride), 4);
img_sv + ISL_IMAGE_PARAM_STRIDE_OFFSET, img,
offsetof(struct isl_image_param, stride), 4);
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_TILING_OFFSET, img,
offsetof(struct brw_image_param, tiling), 3);
img_sv + ISL_IMAGE_PARAM_TILING_OFFSET, img,
offsetof(struct isl_image_param, tiling), 3);
setup_vec4_image_sysval(
img_sv + BRW_IMAGE_PARAM_SWIZZLING_OFFSET, img,
offsetof(struct brw_image_param, swizzling), 2);
img_sv + ISL_IMAGE_PARAM_SWIZZLING_OFFSET, img,
offsetof(struct isl_image_param, swizzling), 2);
}
}
b.cursor = nir_before_instr(instr);
offset = nir_iadd_imm(&b,
get_aoa_deref_offset(&b, deref, BRW_IMAGE_PARAM_SIZE * 4),
get_aoa_deref_offset(&b, deref, ISL_IMAGE_PARAM_SIZE * 4),
system_values_start +
img_idx[var->data.binding] * 4 +
nir_intrinsic_base(intrin) * 16);

14
src/gallium/drivers/iris/iris_state.c
View File

@@ -1532,7 +1532,7 @@ struct iris_genx_state {
struct {
#if GFX_VER == 8
struct brw_image_param image_param[PIPE_MAX_SHADER_IMAGES];
struct isl_image_param image_param[PIPE_MAX_SHADER_IMAGES];
#endif
} shaders[MESA_SHADER_STAGES];
};
@@ -3193,7 +3193,7 @@ iris_create_surface(struct pipe_context *ctx,
#if GFX_VER < 9
static void
fill_default_image_param(struct brw_image_param *param)
fill_default_image_param(struct isl_image_param *param)
{
memset(param, 0, sizeof(*param));
/* Set the swizzling shifts to all-ones to effectively disable swizzling --
@@ -3205,7 +3205,7 @@ fill_default_image_param(struct brw_image_param *param)
}
static void
fill_buffer_image_param(struct brw_image_param *param,
fill_buffer_image_param(struct isl_image_param *param,
enum pipe_format pfmt,
unsigned size)
{
@@ -3237,7 +3237,7 @@ iris_set_shader_images(struct pipe_context *ctx,
struct iris_shader_state *shs = &ice->state.shaders[stage];
#if GFX_VER == 8
struct iris_genx_state *genx = ice->state.genx;
struct brw_image_param *image_params = genx->shaders[stage].image_param;
struct isl_image_param *image_params = genx->shaders[stage].image_param;
#endif
shs->bound_image_views &=
@@ -3351,7 +3351,7 @@ iris_set_shader_images(struct pipe_context *ctx,
stage == MESA_SHADER_COMPUTE ? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
: IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
/* Broadwell also needs brw_image_params re-uploaded */
/* Broadwell also needs isl_image_params re-uploaded */
if (GFX_VER < 9) {
ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_VS << stage;
shs->sysvals_need_upload = true;
@@ -3911,10 +3911,10 @@ upload_sysvals(struct iris_context *ice,
#if GFX_VER == 8
unsigned img = BRW_PARAM_IMAGE_IDX(sysval);
unsigned offset = BRW_PARAM_IMAGE_OFFSET(sysval);
struct brw_image_param *param =
struct isl_image_param *param =
&genx->shaders[stage].image_param[img];
assert(offset < sizeof(struct brw_image_param));
assert(offset < sizeof(struct isl_image_param));
value = ((uint32_t *) param)[offset];
#endif
} else if (sysval == BRW_PARAM_BUILTIN_ZERO) {

43
src/intel/compiler/brw_compiler.h
View File

@@ -27,6 +27,7 @@
#include <stdio.h>
#include "c11/threads.h"
#include "dev/intel_device_info.h"
#include "isl/isl.h"
#include "util/macros.h"
#include "util/enum_operators.h"
#include "util/ralloc.h"
@@ -637,48 +638,6 @@ union brw_any_prog_key {
PRAGMA_DIAGNOSTIC_POP
/*
* Image metadata structure as laid out in the shader parameter
* buffer. Entries have to be 16B-aligned for the vec4 back-end to be
* able to use them. That's okay because the padding and any unused
* entries [most of them except when we're doing untyped surface
* access] will be removed by the uniform packing pass.
*/
#define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
#define BRW_IMAGE_PARAM_SIZE_OFFSET 4
#define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
#define BRW_IMAGE_PARAM_TILING_OFFSET 12
#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
#define BRW_IMAGE_PARAM_SIZE 20
struct brw_image_param {
/** Offset applied to the X and Y surface coordinates. */
uint32_t offset[2];
/** Surface X, Y and Z dimensions. */
uint32_t size[3];
/** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
* pixels, vertical slice stride in pixels.
*/
uint32_t stride[4];
/** Log2 of the tiling modulus in the X, Y and Z dimension. */
uint32_t tiling[3];
/**
* Right shift to apply for bit 6 address swizzling. Two different
* swizzles can be specified and will be applied one after the other. The
* resulting address will be:
*
* addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
* (addr >> swizzling[1])))
*
* Use \c 0xff if any of the swizzles is not required.
*/
uint32_t swizzling[2];
};
/** Max number of render targets in a shader */
#define BRW_MAX_DRAW_BUFFERS 8

12
src/intel/compiler/brw_nir_lower_storage_image.c
View File

@@ -37,15 +37,15 @@ _load_image_param(nir_builder *b, nir_deref_instr *deref, unsigned offset)
nir_intrinsic_set_base(load, offset / 4);
switch (offset) {
case BRW_IMAGE_PARAM_OFFSET_OFFSET:
case BRW_IMAGE_PARAM_SWIZZLING_OFFSET:
case ISL_IMAGE_PARAM_OFFSET_OFFSET:
case ISL_IMAGE_PARAM_SWIZZLING_OFFSET:
load->num_components = 2;
break;
case BRW_IMAGE_PARAM_TILING_OFFSET:
case BRW_IMAGE_PARAM_SIZE_OFFSET:
case ISL_IMAGE_PARAM_TILING_OFFSET:
case ISL_IMAGE_PARAM_SIZE_OFFSET:
load->num_components = 3;
break;
case BRW_IMAGE_PARAM_STRIDE_OFFSET:
case ISL_IMAGE_PARAM_STRIDE_OFFSET:
load->num_components = 4;
break;
default:
@@ -58,7 +58,7 @@ _load_image_param(nir_builder *b, nir_deref_instr *deref, unsigned offset)
}
#define load_image_param(b, d, o) \
_load_image_param(b, d, BRW_IMAGE_PARAM_##o##_OFFSET)
_load_image_param(b, d, ISL_IMAGE_PARAM_##o##_OFFSET)
static nir_def *
image_coord_is_in_bounds(nir_builder *b, nir_deref_instr *deref,

2
src/intel/compiler/brw_vec4_visitor.cpp
View File

@@ -619,7 +619,7 @@ type_size_xvec4(const struct glsl_type *type, bool as_vec4, bool bindless)
case GLSL_TYPE_ATOMIC_UINT:
return 0;
case GLSL_TYPE_IMAGE:
return bindless ? 1 : DIV_ROUND_UP(BRW_IMAGE_PARAM_SIZE, 4);
return bindless ? 1 : DIV_ROUND_UP(ISL_IMAGE_PARAM_SIZE, 4);
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_COOPERATIVE_MATRIX:

47
src/intel/isl/isl.h
View File

@@ -52,7 +52,6 @@ extern "C" {
#endif
struct intel_device_info;
struct brw_image_param;
#ifndef ISL_GFX_VER
/**
@@ -1927,6 +1926,48 @@ struct isl_cpb_emit_info {
uint32_t mocs;
};
/*
* Image metadata structure as laid out in the shader parameter
* buffer. Entries have to be 16B-aligned for the vec4 back-end to be
* able to use them. That's okay because the padding and any unused
* entries [most of them except when we're doing untyped surface
* access] will be removed by the uniform packing pass.
*/
#define ISL_IMAGE_PARAM_OFFSET_OFFSET 0
#define ISL_IMAGE_PARAM_SIZE_OFFSET 4
#define ISL_IMAGE_PARAM_STRIDE_OFFSET 8
#define ISL_IMAGE_PARAM_TILING_OFFSET 12
#define ISL_IMAGE_PARAM_SWIZZLING_OFFSET 16
#define ISL_IMAGE_PARAM_SIZE 20
struct isl_image_param {
/** Offset applied to the X and Y surface coordinates. */
uint32_t offset[2];
/** Surface X, Y and Z dimensions. */
uint32_t size[3];
/** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
* pixels, vertical slice stride in pixels.
*/
uint32_t stride[4];
/** Log2 of the tiling modulus in the X, Y and Z dimension. */
uint32_t tiling[3];
/**
* Right shift to apply for bit 6 address swizzling. Two different
* swizzles can be specified and will be applied one after the other. The
* resulting address will be:
*
* addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
* (addr >> swizzling[1])))
*
* Use \c 0xff if any of the swizzles is not required.
*/
uint32_t swizzling[2];
};
extern const struct isl_format_layout isl_format_layouts[];
extern const char isl_format_names[];
extern const uint16_t isl_format_name_offsets[];
@@ -2684,13 +2725,13 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
void
isl_surf_fill_image_param(const struct isl_device *dev,
struct brw_image_param *param,
struct isl_image_param *param,
const struct isl_surf *surf,
const struct isl_view *view);
void
isl_buffer_fill_image_param(const struct isl_device *dev,
struct brw_image_param *param,
struct isl_image_param *param,
enum isl_format format,
uint64_t size);

6
src/intel/isl/isl_storage_image.c
View File

@@ -243,7 +243,7 @@ isl_has_matching_typed_storage_image_format(const struct intel_device_info *devi
}
}
static const struct brw_image_param image_param_defaults = {
static const struct isl_image_param image_param_defaults = {
/* Set the swizzling shifts to all-ones to effectively disable
* swizzling -- See emit_address_calculation() in
* brw_fs_surface_builder.cpp for a more detailed explanation of
@@ -254,7 +254,7 @@ static const struct brw_image_param image_param_defaults = {
void
isl_surf_fill_image_param(const struct isl_device *dev,
struct brw_image_param *param,
struct isl_image_param *param,
const struct isl_surf *surf,
const struct isl_view *view)
{
@@ -349,7 +349,7 @@ isl_surf_fill_image_param(const struct isl_device *dev,
void
isl_buffer_fill_image_param(const struct isl_device *dev,
struct brw_image_param *param,
struct isl_image_param *param,
enum isl_format format,
uint64_t size)
{

8
src/intel/vulkan_hasvk/anv_descriptor_set.c
View File

@@ -158,7 +158,7 @@ anv_descriptor_data_size(enum anv_descriptor_data data)
size += sizeof(struct anv_storage_image_descriptor);
if (data & ANV_DESCRIPTOR_IMAGE_PARAM)
size += BRW_IMAGE_PARAM_SIZE * 4;
size += ISL_IMAGE_PARAM_SIZE * 4;
if (data & ANV_DESCRIPTOR_ADDRESS_RANGE)
size += sizeof(struct anv_address_range_descriptor);
@@ -1313,11 +1313,11 @@ VkResult anv_FreeDescriptorSets(
static void
anv_descriptor_set_write_image_param(uint32_t *param_desc_map,
const struct brw_image_param *param)
const struct isl_image_param *param)
{
#define WRITE_PARAM_FIELD(field, FIELD) \
for (unsigned i = 0; i < ARRAY_SIZE(param->field); i++) \
param_desc_map[BRW_IMAGE_PARAM_##FIELD##_OFFSET + i] = param->field[i]
param_desc_map[ISL_IMAGE_PARAM_##FIELD##_OFFSET + i] = param->field[i]
WRITE_PARAM_FIELD(offset, OFFSET);
WRITE_PARAM_FIELD(size, SIZE);
@@ -1455,7 +1455,7 @@ anv_descriptor_set_write_image_view(struct anv_device *device,
if (data & ANV_DESCRIPTOR_IMAGE_PARAM) {
/* Storage images can only ever have one plane */
assert(image_view->n_planes == 1);
const struct brw_image_param *image_param =
const struct isl_image_param *image_param =
&image_view->planes[0].lowered_storage_image_param;
anv_descriptor_set_write_image_param(desc_map, image_param);

2
src/intel/vulkan_hasvk/anv_image.c
View File

@@ -2182,7 +2182,7 @@ anv_image_fill_surface_state(struct anv_device *device,
const union isl_color_value *clear_color,
enum anv_image_view_state_flags flags,
struct anv_surface_state *state_inout,
struct brw_image_param *image_param_out)
struct isl_image_param *image_param_out)
{
const uint32_t plane = anv_image_aspect_to_plane(image, aspect);

6
src/intel/vulkan_hasvk/anv_private.h
View File

@@ -1781,7 +1781,7 @@ struct anv_buffer_view {
struct anv_state storage_surface_state;
struct anv_state lowered_storage_surface_state;
struct brw_image_param lowered_storage_image_param;
struct isl_image_param lowered_storage_image_param;
};
struct anv_push_descriptor_set {
@@ -3588,7 +3588,7 @@ struct anv_image_view {
struct anv_surface_state storage_surface_state;
struct anv_surface_state lowered_storage_surface_state;
struct brw_image_param lowered_storage_image_param;
struct isl_image_param lowered_storage_image_param;
} planes[3];
};
@@ -3606,7 +3606,7 @@ void anv_image_fill_surface_state(struct anv_device *device,
const union isl_color_value *clear_color,
enum anv_image_view_state_flags flags,
struct anv_surface_state *state_inout,
struct brw_image_param *image_param_out);
struct isl_image_param *image_param_out);
struct anv_image_create_info {
const VkImageCreateInfo *vk_info;