intel: Sync xe_drm.h
Sync with commit aef50195664a ("drm/xe/uapi: add the userspace bits for small-bar")
Link: https://patchwork.freedesktop.org/series/115515/
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23781>
This commit is contained in:
José Roberto de Souza
committed by
Marge Bot
Marge Bot
parent
a3e3609590
commit
a8279d37ec
@@ -1,26 +1,6 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2021 Intel Corporation. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _UAPI_XE_DRM_H_
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@@ -80,6 +60,7 @@ struct xe_user_extension {
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* Pointer to the next struct xe_user_extension, or zero if the end.
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*/
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__u64 next_extension;
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/**
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* @name: Name of the extension.
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*
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@@ -90,6 +71,7 @@ struct xe_user_extension {
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* of uAPI which has embedded the struct xe_user_extension.
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*/
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__u32 name;
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/**
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* @pad: MBZ
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*
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@@ -125,57 +107,142 @@ struct xe_user_extension {
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#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
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#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
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#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
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#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
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#define DRM_IOCTL_XE_VM_BIND DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
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#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
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#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
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#define DRM_IOCTL_XE_ENGINE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_CREATE, struct drm_xe_engine_create)
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#define DRM_IOCTL_XE_ENGINE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_GET_PROPERTY, struct drm_xe_engine_get_property)
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#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy)
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#define DRM_IOCTL_XE_EXEC DRM_IOW( DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
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#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy)
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#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
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#define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio)
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#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property)
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#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property)
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#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
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#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
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#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
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struct drm_xe_engine_class_instance {
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__u16 engine_class;
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#define DRM_XE_ENGINE_CLASS_RENDER 0
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#define DRM_XE_ENGINE_CLASS_COPY 1
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#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
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#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
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#define DRM_XE_ENGINE_CLASS_COMPUTE 4
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/*
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* Kernel only class (not actual hardware engine class). Used for
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* creating ordered queues of VM bind operations.
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/**
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* enum drm_xe_memory_class - Supported memory classes.
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*/
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enum drm_xe_memory_class {
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/** @XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
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XE_MEM_REGION_CLASS_SYSMEM = 0,
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/**
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* @XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
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* represents the memory that is local to the device, which we
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* call VRAM. Not valid on integrated platforms.
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*/
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#define DRM_XE_ENGINE_CLASS_VM_BIND 5
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__u16 engine_instance;
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__u16 gt_id;
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XE_MEM_REGION_CLASS_VRAM
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};
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#define XE_MEM_REGION_CLASS_SYSMEM 0
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#define XE_MEM_REGION_CLASS_VRAM 1
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/**
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* struct drm_xe_query_mem_region - Describes some region as known to
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* the driver.
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*/
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struct drm_xe_query_mem_region {
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/**
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* @mem_class: The memory class describing this region.
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*
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* See enum drm_xe_memory_class for supported values.
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*/
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__u16 mem_class;
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/**
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* @instance: The instance for this region.
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*
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* The @mem_class and @instance taken together will always give
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* a unique pair.
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*/
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__u16 instance;
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/** @pad: MBZ */
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__u32 pad;
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/**
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* @min_page_size: Min page-size in bytes for this region.
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*
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* When the kernel allocates memory for this region, the
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* underlying pages will be at least @min_page_size in size.
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*
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* Important note: When userspace allocates a GTT address which
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* can point to memory allocated from this region, it must also
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* respect this minimum alignment. This is enforced by the
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* kernel.
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*/
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__u32 min_page_size;
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/**
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* @max_page_size: Max page-size in bytes for this region.
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*/
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__u32 max_page_size;
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/**
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* @total_size: The usable size in bytes for this region.
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*/
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__u64 total_size;
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/**
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* @used: Estimate of the memory used in bytes for this region.
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*
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* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
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* accounting. Without this the value here will always equal
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* zero.
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*/
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__u64 used;
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/**
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* @cpu_visible_size: How much of this region can be CPU
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* accessed, in bytes.
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*
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* This will always be <= @total_size, and the remainder (if
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* any) will not be CPU accessible. If the CPU accessible part
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* is smaller than @total_size then this is referred to as a
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* small BAR system.
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*
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* On systems without small BAR (full BAR), the probed_size will
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* always equal the @total_size, since all of it will be CPU
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* accessible.
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*
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* Note this is only tracked for XE_MEM_REGION_CLASS_VRAM
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* regions (for other types the value here will always equal
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* zero).
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*/
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__u64 cpu_visible_size;
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/**
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* @cpu_visible_used: Estimate of CPU visible memory used, in
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* bytes.
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*
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* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
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* accounting. Without this the value here will always equal
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* zero. Note this is only currently tracked for
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* XE_MEM_REGION_CLASS_VRAM regions (for other types the value
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* here will always be zero).
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*/
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__u64 cpu_visible_used;
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/** @reserved: MBZ */
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__u64 reserved[6];
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};
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/**
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* struct drm_xe_query_mem_usage - describe memory regions and usage
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*
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* If a query is made with a struct drm_xe_device_query where .query
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* is equal to DRM_XE_DEVICE_QUERY_MEM_USAGE, then the reply uses
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* struct drm_xe_query_mem_usage in .data.
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*/
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struct drm_xe_query_mem_usage {
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/** @num_regions: number of memory regions returned in @regions */
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__u32 num_regions;
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/** @pad: MBZ */
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__u32 pad;
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struct drm_xe_query_mem_region {
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__u16 mem_class;
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__u16 instance; /* unique ID even among different classes */
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__u32 pad;
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__u32 min_page_size;
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__u32 max_page_size;
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__u64 total_size;
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__u64 used;
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__u64 reserved[8];
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} regions[];
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/** @regions: The returned regions for this device */
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struct drm_xe_query_mem_region regions[];
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};
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/**
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* struct drm_xe_query_config - describe the device configuration
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*
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* If a query is made with a struct drm_xe_device_query where .query
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* is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
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* struct drm_xe_query_config in .data.
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*/
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struct drm_xe_query_config {
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/** @num_params: number of parameters returned in info */
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__u32 num_params;
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/** @pad: MBZ */
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__u32 pad;
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#define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
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#define XE_QUERY_CONFIG_FLAGS 1
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#define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
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@@ -185,19 +252,32 @@ struct drm_xe_query_config {
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#define XE_QUERY_CONFIG_GT_COUNT 4
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#define XE_QUERY_CONFIG_MEM_REGION_COUNT 5
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#define XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY 6
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#define XE_QUERY_CONFIG_NUM_PARAM XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY + 1
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#define XE_QUERY_CONFIG_NUM_PARAM (XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY + 1)
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/** @info: array of elements containing the config info */
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__u64 info[];
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};
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/**
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* struct drm_xe_query_gts - describe GTs
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*
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* If a query is made with a struct drm_xe_device_query where .query
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* is equal to DRM_XE_DEVICE_QUERY_GTS, then the reply uses struct
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* drm_xe_query_gts in .data.
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*/
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struct drm_xe_query_gts {
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/** @num_gt: number of GTs returned in gts */
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__u32 num_gt;
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/** @pad: MBZ */
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__u32 pad;
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/*
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/**
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* @gts: The GTs returned for this device
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*
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* TODO: convert drm_xe_query_gt to proper kernel-doc.
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* TODO: Perhaps info about every mem region relative to this GT? e.g.
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* bandwidth between this GT and remote region?
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*/
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struct drm_xe_query_gt {
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#define XE_QUERY_GT_TYPE_MAIN 0
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#define XE_QUERY_GT_TYPE_REMOTE 1
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@@ -213,15 +293,46 @@ struct drm_xe_query_gts {
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} gts[];
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};
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/**
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* struct drm_xe_query_topology_mask - describe the topology mask of a GT
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*
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* This is the hardware topology which reflects the internal physical
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* structure of the GPU.
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*
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* If a query is made with a struct drm_xe_device_query where .query
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* is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
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* struct drm_xe_query_topology_mask in .data.
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*/
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struct drm_xe_query_topology_mask {
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/** @gt_id: GT ID the mask is associated with */
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__u16 gt_id;
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/*
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* To query the mask of Dual Sub Slices (DSS) available for geometry
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* operations. For example a query response containing the following
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* in mask:
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* DSS_GEOMETRY ff ff ff ff 00 00 00 00
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* means 32 DSS are available for geometry.
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*/
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#define XE_TOPO_DSS_GEOMETRY (1 << 0)
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/*
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* To query the mask of Dual Sub Slices (DSS) available for compute
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* operations. For example a query response containing the following
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* in mask:
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* DSS_COMPUTE ff ff ff ff 00 00 00 00
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* means 32 DSS are available for compute.
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*/
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#define XE_TOPO_DSS_COMPUTE (1 << 1)
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/*
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* To query the mask of Execution Units (EU) available per Dual Sub
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* Slices (DSS). For example a query response containing the following
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* in mask:
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* EU_PER_DSS ff ff 00 00 00 00 00 00
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* means each DSS has 16 EU.
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*/
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#define XE_TOPO_EU_PER_DSS (1 << 2)
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/** @type: type of mask */
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__u16 type;
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#define XE_TOPO_DSS_GEOMETRY (1 << 0)
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#define XE_TOPO_DSS_COMPUTE (1 << 1)
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#define XE_TOPO_EU_PER_DSS (1 << 2)
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/** @num_bytes: number of bytes in requested mask */
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__u32 num_bytes;
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@@ -230,19 +341,53 @@ struct drm_xe_query_topology_mask {
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__u8 mask[];
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};
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/**
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* struct drm_xe_device_query - main structure to query device information
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*
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* If size is set to 0, the driver fills it with the required size for the
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* requested type of data to query. If size is equal to the required size,
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* the queried information is copied into data.
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*
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* For example the following code snippet allows retrieving and printing
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* information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
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*
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* .. code-block:: C
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*
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* struct drm_xe_engine_class_instance *hwe;
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* struct drm_xe_device_query query = {
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* .extensions = 0,
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* .query = DRM_XE_DEVICE_QUERY_ENGINES,
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* .size = 0,
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* .data = 0,
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* };
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* ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
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* hwe = malloc(query.size);
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* query.data = (uintptr_t)hwe;
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* ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
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* int num_engines = query.size / sizeof(*hwe);
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* for (int i = 0; i < num_engines; i++) {
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* printf("Engine %d: %s\n", i,
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* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER":
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* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY":
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* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE":
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* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE":
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* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE":
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* "UNKNOWN");
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* }
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* free(hwe);
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*/
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struct drm_xe_device_query {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @query: The type of data to query */
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__u32 query;
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#define DRM_XE_DEVICE_QUERY_ENGINES 0
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#define DRM_XE_DEVICE_QUERY_MEM_USAGE 1
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#define DRM_XE_DEVICE_QUERY_CONFIG 2
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#define DRM_XE_DEVICE_QUERY_GTS 3
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#define DRM_XE_DEVICE_QUERY_HWCONFIG 4
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#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
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/** @query: The type of data to query */
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__u32 query;
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/** @size: Size of the queried data */
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__u32 size;
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@@ -265,12 +410,28 @@ struct drm_xe_gem_create {
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*/
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__u64 size;
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#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
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#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
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/*
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* When using VRAM as a possible placement, ensure that the corresponding VRAM
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* allocation will always use the CPU accessible part of VRAM. This is important
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* for small-bar systems (on full-bar systems this gets turned into a noop).
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*
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* Note: System memory can be used as an extra placement if the kernel should
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* spill the allocation to system memory, if space can't be made available in
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* the CPU accessible part of VRAM (giving the same behaviour as the i915
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* interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
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*
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* Note: For clear-color CCS surfaces the kernel needs to read the clear-color
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* value stored in the buffer, and on discrete platforms we need to use VRAM for
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* display surfaces, therefore the kernel requires setting this flag for such
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* objects, otherwise an error is thrown on small-bar systems.
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*/
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#define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
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/**
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* @flags: Flags, currently a mask of memory instances of where BO can
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* be placed
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*/
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#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
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#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
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__u32 flags;
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||||
|
||||
/**
|
||||
@@ -321,10 +482,13 @@ struct drm_xe_gem_mmap_offset {
|
||||
struct drm_xe_vm_bind_op_error_capture {
|
||||
/** @error: errno that occured */
|
||||
__s32 error;
|
||||
|
||||
/** @op: operation that encounter an error */
|
||||
__u32 op;
|
||||
|
||||
/** @addr: address of bind op */
|
||||
__u64 addr;
|
||||
|
||||
/** @size: size of bind */
|
||||
__u64 size;
|
||||
};
|
||||
@@ -334,8 +498,8 @@ struct drm_xe_ext_vm_set_property {
|
||||
/** @base: base user extension */
|
||||
struct xe_user_extension base;
|
||||
|
||||
/** @property: property to set */
|
||||
#define XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS 0
|
||||
/** @property: property to set */
|
||||
__u32 property;
|
||||
|
||||
/** @pad: MBZ */
|
||||
@@ -349,17 +513,16 @@ struct drm_xe_ext_vm_set_property {
|
||||
};
|
||||
|
||||
struct drm_xe_vm_create {
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
#define XE_VM_EXTENSION_SET_PROPERTY 0
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
__u64 extensions;
|
||||
|
||||
/** @flags: Flags */
|
||||
__u32 flags;
|
||||
|
||||
#define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
|
||||
#define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
|
||||
#define DRM_XE_VM_CREATE_ASYNC_BIND_OPS (0x1 << 2)
|
||||
#define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
|
||||
/** @flags: Flags */
|
||||
__u32 flags;
|
||||
|
||||
/** @vm_id: Returned VM ID */
|
||||
__u32 vm_id;
|
||||
@@ -394,6 +557,7 @@ struct drm_xe_vm_bind_op {
|
||||
* ignored for unbind
|
||||
*/
|
||||
__u64 obj_offset;
|
||||
|
||||
/** @userptr: user pointer to bind on */
|
||||
__u64 userptr;
|
||||
};
|
||||
@@ -407,16 +571,10 @@ struct drm_xe_vm_bind_op {
|
||||
__u64 addr;
|
||||
|
||||
/**
|
||||
* @gt_mask: Mask for which GTs to create binds for, 0 == All GTs,
|
||||
* @tile_mask: Mask for which tiles to create binds for, 0 == All tiles,
|
||||
* only applies to creating new VMAs
|
||||
*/
|
||||
__u64 gt_mask;
|
||||
|
||||
/** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
|
||||
__u32 op;
|
||||
|
||||
/** @mem_region: Memory region to prefetch VMA to, instance not a mask */
|
||||
__u32 region;
|
||||
__u64 tile_mask;
|
||||
|
||||
#define XE_VM_BIND_OP_MAP 0x0
|
||||
#define XE_VM_BIND_OP_UNMAP 0x1
|
||||
@@ -437,8 +595,8 @@ struct drm_xe_vm_bind_op {
|
||||
* If this flag is clear and the IOCTL doesn't return an error, in
|
||||
* practice the bind op is good and will complete.
|
||||
*
|
||||
* If this flag is set and doesn't return return an error, the bind op
|
||||
* can still fail and recovery is needed. If configured, the bind op that
|
||||
* If this flag is set and doesn't return an error, the bind op can
|
||||
* still fail and recovery is needed. If configured, the bind op that
|
||||
* caused the error will be captured in drm_xe_vm_bind_op_error_capture.
|
||||
* Once the user sees the error (via a ufence +
|
||||
* XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS), it should free memory
|
||||
@@ -456,6 +614,19 @@ struct drm_xe_vm_bind_op {
|
||||
* than differing the MAP to the page fault handler.
|
||||
*/
|
||||
#define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 18)
|
||||
/*
|
||||
* When the NULL flag is set, the page tables are setup with a special
|
||||
* bit which indicates writes are dropped and all reads return zero. In
|
||||
* the future, the NULL flags will only be valid for XE_VM_BIND_OP_MAP
|
||||
* operations, the BO handle MBZ, and the BO offset MBZ. This flag is
|
||||
* intended to implement VK sparse bindings.
|
||||
*/
|
||||
#define XE_VM_BIND_FLAG_NULL (0x1 << 19)
|
||||
/** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
|
||||
__u32 op;
|
||||
|
||||
/** @mem_region: Memory region to prefetch VMA to, instance not a mask */
|
||||
__u32 region;
|
||||
|
||||
/** @reserved: Reserved */
|
||||
__u64 reserved[2];
|
||||
@@ -484,6 +655,7 @@ struct drm_xe_vm_bind {
|
||||
union {
|
||||
/** @bind: used if num_binds == 1 */
|
||||
struct drm_xe_vm_bind_op bind;
|
||||
|
||||
/**
|
||||
* @vector_of_binds: userptr to array of struct
|
||||
* drm_xe_vm_bind_op if num_binds > 1
|
||||
@@ -531,7 +703,6 @@ struct drm_xe_engine_set_property {
|
||||
/** @engine_id: Engine ID */
|
||||
__u32 engine_id;
|
||||
|
||||
/** @property: property to set */
|
||||
#define XE_ENGINE_SET_PROPERTY_PRIORITY 0
|
||||
#define XE_ENGINE_SET_PROPERTY_TIMESLICE 1
|
||||
#define XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
|
||||
@@ -547,6 +718,7 @@ struct drm_xe_engine_set_property {
|
||||
#define XE_ENGINE_SET_PROPERTY_ACC_TRIGGER 6
|
||||
#define XE_ENGINE_SET_PROPERTY_ACC_NOTIFY 7
|
||||
#define XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY 8
|
||||
/** @property: property to set */
|
||||
__u32 property;
|
||||
|
||||
/** @value: property value */
|
||||
@@ -556,9 +728,27 @@ struct drm_xe_engine_set_property {
|
||||
__u64 reserved[2];
|
||||
};
|
||||
|
||||
/** struct drm_xe_engine_class_instance - instance of an engine class */
|
||||
struct drm_xe_engine_class_instance {
|
||||
#define DRM_XE_ENGINE_CLASS_RENDER 0
|
||||
#define DRM_XE_ENGINE_CLASS_COPY 1
|
||||
#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
|
||||
#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
|
||||
#define DRM_XE_ENGINE_CLASS_COMPUTE 4
|
||||
/*
|
||||
* Kernel only class (not actual hardware engine class). Used for
|
||||
* creating ordered queues of VM bind operations.
|
||||
*/
|
||||
#define DRM_XE_ENGINE_CLASS_VM_BIND 5
|
||||
__u16 engine_class;
|
||||
|
||||
__u16 engine_instance;
|
||||
__u16 gt_id;
|
||||
};
|
||||
|
||||
struct drm_xe_engine_create {
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
#define XE_ENGINE_EXTENSION_SET_PROPERTY 0
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
__u64 extensions;
|
||||
|
||||
/** @width: submission width (number BB per exec) for this engine */
|
||||
@@ -596,8 +786,8 @@ struct drm_xe_engine_get_property {
|
||||
/** @engine_id: Engine ID */
|
||||
__u32 engine_id;
|
||||
|
||||
/** @property: property to get */
|
||||
#define XE_ENGINE_GET_PROPERTY_BAN 0
|
||||
/** @property: property to get */
|
||||
__u32 property;
|
||||
|
||||
/** @value: property value */
|
||||
@@ -622,19 +812,19 @@ struct drm_xe_sync {
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
__u64 extensions;
|
||||
|
||||
__u32 flags;
|
||||
|
||||
#define DRM_XE_SYNC_SYNCOBJ 0x0
|
||||
#define DRM_XE_SYNC_TIMELINE_SYNCOBJ 0x1
|
||||
#define DRM_XE_SYNC_DMA_BUF 0x2
|
||||
#define DRM_XE_SYNC_USER_FENCE 0x3
|
||||
#define DRM_XE_SYNC_SIGNAL 0x10
|
||||
__u32 flags;
|
||||
|
||||
/** @pad: MBZ */
|
||||
__u32 pad;
|
||||
|
||||
union {
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @addr: Address of user fence. When sync passed in via exec
|
||||
* IOCTL this a GPU address in the VM. When sync passed in via
|
||||
@@ -656,7 +846,7 @@ struct drm_xe_exec {
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
__u64 extensions;
|
||||
|
||||
/** @vm_id: VM ID to run batch buffer in */
|
||||
/** @engine_id: Engine ID for the batch buffer */
|
||||
__u32 engine_id;
|
||||
|
||||
/** @num_syncs: Amount of struct drm_xe_sync in array. */
|
||||
@@ -666,9 +856,9 @@ struct drm_xe_exec {
|
||||
__u64 syncs;
|
||||
|
||||
/**
|
||||
* @address: address of batch buffer if num_batch_buffer == 1 or an
|
||||
* array of batch buffer addresses
|
||||
*/
|
||||
* @address: canonical address of batch buffer if num_batch_buffer == 1
|
||||
* or an array of batch buffer canonical addresses
|
||||
*/
|
||||
__u64 address;
|
||||
|
||||
/**
|
||||
@@ -690,8 +880,6 @@ struct drm_xe_mmio {
|
||||
|
||||
__u32 addr;
|
||||
|
||||
__u32 flags;
|
||||
|
||||
#define DRM_XE_MMIO_8BIT 0x0
|
||||
#define DRM_XE_MMIO_16BIT 0x1
|
||||
#define DRM_XE_MMIO_32BIT 0x2
|
||||
@@ -699,6 +887,7 @@ struct drm_xe_mmio {
|
||||
#define DRM_XE_MMIO_BITS_MASK 0x3
|
||||
#define DRM_XE_MMIO_READ 0x4
|
||||
#define DRM_XE_MMIO_WRITE 0x8
|
||||
__u32 flags;
|
||||
|
||||
__u64 value;
|
||||
|
||||
@@ -710,55 +899,78 @@ struct drm_xe_mmio {
|
||||
* struct drm_xe_wait_user_fence - wait user fence
|
||||
*
|
||||
* Wait on user fence, XE will wakeup on every HW engine interrupt in the
|
||||
* instances list and check if user fence is complete:
|
||||
* (*addr & MASK) OP (VALUE & MASK)
|
||||
* instances list and check if user fence is complete::
|
||||
*
|
||||
* (*addr & MASK) OP (VALUE & MASK)
|
||||
*
|
||||
* Returns to user on user fence completion or timeout.
|
||||
*/
|
||||
struct drm_xe_wait_user_fence {
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
__u64 extensions;
|
||||
|
||||
union {
|
||||
/**
|
||||
* @addr: user pointer address to wait on, must qword aligned
|
||||
*/
|
||||
__u64 addr;
|
||||
|
||||
/**
|
||||
* @vm_id: The ID of the VM which encounter an error used with
|
||||
* DRM_XE_UFENCE_WAIT_VM_ERROR. Upper 32 bits must be clear.
|
||||
*/
|
||||
__u64 vm_id;
|
||||
};
|
||||
/** @op: wait operation (type of comparison) */
|
||||
|
||||
#define DRM_XE_UFENCE_WAIT_EQ 0
|
||||
#define DRM_XE_UFENCE_WAIT_NEQ 1
|
||||
#define DRM_XE_UFENCE_WAIT_GT 2
|
||||
#define DRM_XE_UFENCE_WAIT_GTE 3
|
||||
#define DRM_XE_UFENCE_WAIT_LT 4
|
||||
#define DRM_XE_UFENCE_WAIT_LTE 5
|
||||
/** @op: wait operation (type of comparison) */
|
||||
__u16 op;
|
||||
/** @flags: wait flags */
|
||||
|
||||
#define DRM_XE_UFENCE_WAIT_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
|
||||
#define DRM_XE_UFENCE_WAIT_ABSTIME (1 << 1)
|
||||
#define DRM_XE_UFENCE_WAIT_VM_ERROR (1 << 2)
|
||||
/** @flags: wait flags */
|
||||
__u16 flags;
|
||||
|
||||
/** @pad: MBZ */
|
||||
__u32 pad;
|
||||
|
||||
/** @value: compare value */
|
||||
__u64 value;
|
||||
/** @mask: comparison mask */
|
||||
|
||||
#define DRM_XE_UFENCE_WAIT_U8 0xffu
|
||||
#define DRM_XE_UFENCE_WAIT_U16 0xffffu
|
||||
#define DRM_XE_UFENCE_WAIT_U32 0xffffffffu
|
||||
#define DRM_XE_UFENCE_WAIT_U64 0xffffffffffffffffu
|
||||
/** @mask: comparison mask */
|
||||
__u64 mask;
|
||||
/** @timeout: how long to wait before bailing, value in jiffies */
|
||||
/**
|
||||
* @timeout: how long to wait before bailing, value in nanoseconds.
|
||||
* Without DRM_XE_UFENCE_WAIT_ABSTIME flag set (relative timeout)
|
||||
* it contains timeout expressed in nanoseconds to wait (fence will
|
||||
* expire at now() + timeout).
|
||||
* When DRM_XE_UFENCE_WAIT_ABSTIME flat is set (absolute timeout) wait
|
||||
* will end at timeout (uses system MONOTONIC_CLOCK).
|
||||
* Passing negative timeout leads to neverending wait.
|
||||
*
|
||||
* On relative timeout this value is updated with timeout left
|
||||
* (for restarting the call in case of signal delivery).
|
||||
* On absolute timeout this value stays intact (restarted call still
|
||||
* expire at the same point of time).
|
||||
*/
|
||||
__s64 timeout;
|
||||
|
||||
/**
|
||||
* @num_engines: number of engine instances to wait on, must be zero
|
||||
* when DRM_XE_UFENCE_WAIT_SOFT_OP set
|
||||
*/
|
||||
__u64 num_engines;
|
||||
|
||||
/**
|
||||
* @instances: user pointer to array of drm_xe_engine_class_instance to
|
||||
* wait on, must be NULL when DRM_XE_UFENCE_WAIT_SOFT_OP set
|
||||
@@ -789,6 +1001,9 @@ struct drm_xe_vm_madvise {
|
||||
* Setting the preferred location will trigger a migrate of the VMA
|
||||
* backing store to new location if the backing store is already
|
||||
* allocated.
|
||||
*
|
||||
* For DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS usage, see enum
|
||||
* drm_xe_memory_class.
|
||||
*/
|
||||
#define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS 0
|
||||
#define DRM_XE_VM_MADVISE_PREFERRED_GT 1
|
||||
@@ -819,7 +1034,6 @@ struct drm_xe_vm_madvise {
|
||||
#define DRM_XE_VMA_PRIORITY_HIGH 2 /* Must be elevated user */
|
||||
/* Pin the VMA in memory, must be elevated user */
|
||||
#define DRM_XE_VM_MADVISE_PIN 6
|
||||
|
||||
/** @property: property to set */
|
||||
__u32 property;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user