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radv: don't assume that TC_ACTION_ENA invalidates L1 cache on gfx9

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Ported from RadeonSI 279315fd73 ("radeonsi: don't assume that
TC_ACTION_ENA invalidates L1 cache on gfx9")

Thanks to Rhys for noticing this by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29644>
This commit is contained in:
Samuel Pitoiset
2024-06-10 12:11:53 +02:00
committed by Marge Bot
parent e7615a612f
commit a80a1c9838
1 changed files with 3 additions and 3 deletions
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6
src/amd/vulkan/radv_cs.c
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@@ -458,7 +458,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enu
* All operations that invalidate L2 also seem to invalidate
* metadata. Volatile (VOL) and WC flushes are not listed here.
*
* TC | TC_WB = writeback & invalidate L2 & L1
* TC | TC_WB = writeback & invalidate L2
* TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
* TC_WB | TC_NC = writeback L2 for MTYPE == NC
* TC | TC_NC = invalidate L2 for MTYPE == NC
@@ -471,11 +471,11 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enu
/* Ideally flush TC together with CB/DB. */
if (flush_bits & RADV_CMD_FLAG_INV_L2) {
/* Writeback and invalidate everything in L2 & L1. */
/* Writeback and invalidate everything in L2. */
tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_WB_ACTION_ENA;
/* Clear the flags. */
flush_bits &= ~(RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_WB_L2 | RADV_CMD_FLAG_INV_VCACHE);
flush_bits &= ~(RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_WB_L2);
*sqtt_flush_bits |= RGP_FLUSH_INVAL_L2;
}