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radv: rework considering force VRS without relying on graphics pipeline

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24313>
This commit is contained in:
Samuel Pitoiset
2023-07-24 16:35:49 +02:00
committed by Marge Bot
parent 9d89b29a80
commit a7fdcc3b22
3 changed files with 23 additions and 15 deletions
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5
src/amd/vulkan/radv_pipeline.c
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@@ -626,10 +626,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
}
/* Lower I/O intrinsics to memory instructions. */
bool is_last_vgt_stage =
(stage->info.stage == MESA_SHADER_VERTEX || stage->info.stage == MESA_SHADER_TESS_EVAL ||
stage->info.stage == MESA_SHADER_GEOMETRY || stage->info.stage == MESA_SHADER_MESH) &&
(stage->info.next_stage == MESA_SHADER_FRAGMENT || stage->info.next_stage == MESA_SHADER_NONE);
bool is_last_vgt_stage = radv_is_last_vgt_stage(stage);
bool io_to_mem = radv_nir_lower_io_to_mem(device, stage);
bool lowered_ngg = stage->info.is_ngg && is_last_vgt_stage;
if (lowered_ngg) {