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intel/vec4/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.

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Rework:
 * Jordan: 16=>20 following d33aff783d ("intel/fs: add support for
   sparse accesses")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Francisco Jerez
2022-02-18 22:28:58 -08:00
committed by Jordan Justen
parent 5d87f41a54
commit a7d521e556
1 changed files with 7 additions and 5 deletions
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12
src/intel/compiler/brw_vec4_reg_allocate.cpp
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@@ -27,6 +27,8 @@
using namespace brw;
#define REG_CLASS_COUNT 20
namespace brw {
static void
@@ -100,10 +102,10 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
* SEND-from-GRF sources cannot be split, so we also need classes for each
* potential message length.
*/
const int class_count = MAX_VGRF_SIZE;
int class_sizes[MAX_VGRF_SIZE];
assert(REG_CLASS_COUNT == MAX_VGRF_SIZE);
int class_sizes[REG_CLASS_COUNT];
for (int i = 0; i < class_count; i++)
for (int i = 0; i < REG_CLASS_COUNT; i++)
class_sizes[i] = i + 1;
@@ -112,12 +114,12 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
if (compiler->devinfo->ver >= 6)
ra_set_allocate_round_robin(compiler->vec4_reg_set.regs);
ralloc_free(compiler->vec4_reg_set.classes);
compiler->vec4_reg_set.classes = ralloc_array(compiler, struct ra_class *, class_count);
compiler->vec4_reg_set.classes = ralloc_array(compiler, struct ra_class *, REG_CLASS_COUNT);
/* Now, add the registers to their classes, and add the conflicts
* between them and the base GRF registers (and also each other).
*/
for (int i = 0; i < class_count; i++) {
for (int i = 0; i < REG_CLASS_COUNT; i++) {
int class_reg_count = base_reg_count - (class_sizes[i] - 1);
compiler->vec4_reg_set.classes[i] =
ra_alloc_contig_reg_class(compiler->vec4_reg_set.regs, class_sizes[i]);