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iris: Make the D16 reg mode single-sampled

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Wa_14010455700 is dependent on the format and sample count, but our
code to track whether or not it had been applied was only dependent on
the format.

As a result, we failed to enable the workaround when an app used a D16
2xMSAA buffer, then a D16 1xMSAA buffer right afterwards.

Make the workaround tracking code sample-dependent to fix this.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
This commit is contained in:
Nanley Chery
2022-08-01 14:13:46 -07:00
committed by Marge Bot
parent e7419c11ae
commit a75cd15b94
1 changed files with 9 additions and 7 deletions
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16
src/gallium/drivers/iris/iris_state.c
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@@ -1219,7 +1219,7 @@ struct iris_depth_buffer_state {
#if GFX_VERx10 == 120 #if GFX_VERx10 == 120
enum iris_depth_reg_mode { enum iris_depth_reg_mode {
IRIS_DEPTH_REG_MODE_HW_DEFAULT = 0, IRIS_DEPTH_REG_MODE_HW_DEFAULT = 0,
IRIS_DEPTH_REG_MODE_D16, IRIS_DEPTH_REG_MODE_D16_1X_MSAA,
IRIS_DEPTH_REG_MODE_UNKNOWN, IRIS_DEPTH_REG_MODE_UNKNOWN,
}; };
#endif #endif
@@ -5722,15 +5722,16 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice,
const struct isl_surf *surf) const struct isl_surf *surf)
{ {
#if GFX_VERx10 == 120 #if GFX_VERx10 == 120
const bool fmt_is_d16 = surf->format == ISL_FORMAT_R16_UNORM; const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM &&
surf->samples == 1;
switch (ice->state.genx->depth_reg_mode) { switch (ice->state.genx->depth_reg_mode) {
case IRIS_DEPTH_REG_MODE_HW_DEFAULT: case IRIS_DEPTH_REG_MODE_HW_DEFAULT:
if (!fmt_is_d16) if (!is_d16_1x_msaa)
return; return;
break; break;
case IRIS_DEPTH_REG_MODE_D16: case IRIS_DEPTH_REG_MODE_D16_1X_MSAA:
if (fmt_is_d16) if (is_d16_1x_msaa)
return; return;
break; break;
case IRIS_DEPTH_REG_MODE_UNKNOWN: case IRIS_DEPTH_REG_MODE_UNKNOWN:
@@ -5752,12 +5753,13 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice,
* Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”. * Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.
*/ */
iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), reg) { iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), reg) {
reg.HIZPlaneOptimizationdisablebit = fmt_is_d16 && surf->samples == 1; reg.HIZPlaneOptimizationdisablebit = is_d16_1x_msaa;
reg.HIZPlaneOptimizationdisablebitMask = true; reg.HIZPlaneOptimizationdisablebitMask = true;
} }
ice->state.genx->depth_reg_mode = ice->state.genx->depth_reg_mode =
fmt_is_d16 ? IRIS_DEPTH_REG_MODE_D16 : IRIS_DEPTH_REG_MODE_HW_DEFAULT; is_d16_1x_msaa ? IRIS_DEPTH_REG_MODE_D16_1X_MSAA :
IRIS_DEPTH_REG_MODE_HW_DEFAULT;
#endif #endif
} }