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intel/perf: prep work to enable new perf counters

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Those are not part of the OA reports and need some additional
scaffolding. Those counters are only available when doing queries as
we need to emit MI_SRMs to record them.

Equations making use of those counters are not there yet, they will
come in a follow up commit updating a bunch of oa-*.xml files.

v2: Fix typo

v3: Use PERF_CNT_VALUE_MASK (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
This commit is contained in:
Lionel Landwerlin
2019-07-04 20:34:28 +03:00
committed by Marge Bot
parent 969f6efbc2
commit a6e980e9bf
8 changed files with 72 additions and 61 deletions
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16
src/intel/vulkan/genX_query.c
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@@ -326,7 +326,7 @@ intel_perf_rpstart_offset(bool end)
return 16 + (end ? sizeof(uint32_t) : 0);
}
#if GEN_GEN >= 8 && GEN_GEN <= 11
#if GEN_IS_HASWELL || (GEN_GEN >= 8 && GEN_GEN <= 11)
static uint32_t
intel_perf_counter(bool end)
{
@@ -541,14 +541,14 @@ VkResult genX(GetQueryPoolResults)(
oa_begin, oa_end);
gen_perf_query_result_read_gt_frequency(&result, &device->info,
*rpstat_begin, *rpstat_end);
gen_perf_query_result_write_mdapi(pData, stride,
&device->info,
query, &result);
#if GEN_GEN >= 8 && GEN_GEN <= 11
gen_perf_query_mdapi_write_perfcntr(pData, stride, &device->info,
#if GEN_IS_HASWELL || (GEN_GEN >= 8 && GEN_GEN <= 11)
gen_perf_query_result_read_perfcnts(&result, query,
query_data + intel_perf_counter(false),
query_data + intel_perf_counter(true));
#endif
gen_perf_query_result_write_mdapi(pData, stride,
&device->info,
query, &result);
const uint64_t *marker = query_data + intel_perf_marker_offset();
gen_perf_query_mdapi_write_marker(pData, stride, &device->info, *marker);
break;
@@ -913,7 +913,7 @@ void genX(CmdBeginQueryIndexedEXT)(
intel_perf_rpstart_offset(false))),
gen_mi_reg32(GENX(RPSTAT0_num)));
#endif
#if GEN_GEN >= 8 && GEN_GEN <= 11
#if GEN_IS_HASWELL || (GEN_GEN >= 8 && GEN_GEN <= 11)
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr,
intel_perf_counter(false))),
gen_mi_reg64(GENX(PERFCNT1_num)));
@@ -1047,7 +1047,7 @@ void genX(CmdEndQueryIndexedEXT)(
uint32_t marker_offset = intel_perf_marker_offset();
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr, marker_offset)),
gen_mi_imm(cmd_buffer->intel_perf_marker));
#if GEN_GEN >= 8 && GEN_GEN <= 11
#if GEN_IS_HASWELL || (GEN_GEN >= 8 && GEN_GEN <= 11)
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr, intel_perf_counter(true))),
gen_mi_reg64(GENX(PERFCNT1_num)));
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr, intel_perf_counter(true) + 8)),