From a6c6a4ad04d5e70b32c6e87126a4e8779aa6bb93 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 5 Jan 2023 11:13:12 -0800 Subject: [PATCH] intel/blorp: Lower base_workgroup_id to zero We don't use a base workgroup ID for BLOCS. It needs to be lowered, or else we'll assert fail when compiling the compute shader. (Note for stable: this patch doesn't fix a bug in 4abdecce226 specifically, but rather is a missing patch that needed to go along with the rest of MR 20068, on whichever branches it exists on.) Fixes: 4abdecce226 ("iris: Lower load_base_workgroup_id to zero") Reviewed-by: Jason Ekstrand Part-of: --- src/intel/blorp/blorp.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index 245baaa7462..69dcfbfc3f6 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -348,6 +348,22 @@ blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx, return brw_compile_vs(compiler, mem_ctx, ¶ms); } +static bool +lower_base_workgroup_id(nir_builder *b, nir_instr *instr, UNUSED void *data) +{ + if (instr->type != nir_instr_type_intrinsic) + return false; + + nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); + + if (intrin->intrinsic != nir_intrinsic_load_base_workgroup_id) + return false; + + b->cursor = nir_instr_remove(&intrin->instr); + nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_imm_zero(b, 3, 32)); + return true; +} + const unsigned * blorp_compile_cs(struct blorp_context *blorp, void *mem_ctx, struct nir_shader *nir, @@ -375,6 +391,8 @@ blorp_compile_cs(struct blorp_context *blorp, void *mem_ctx, cs_prog_data->base.param = rzalloc_array(NULL, uint32_t, nr_params); NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics); + NIR_PASS_V(nir, nir_shader_instructions_pass, lower_base_workgroup_id, + nir_metadata_block_index | nir_metadata_dominance, NULL); struct brw_compile_cs_params params = { .nir = nir,