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intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units.

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Francisco Jerez
2022-07-19 16:44:26 -07:00
committed by Jordan Justen
parent 17ef5e7ead
commit a573531785
6 changed files with 27 additions and 7 deletions
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15
src/intel/compiler/brw_fs.cpp
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@@ -7875,7 +7875,10 @@ brw_compile_fs(const struct brw_compiler *compiler,
return NULL;
} else if (INTEL_SIMD(FS, 8)) {
simd8_cfg = v8->cfg;
prog_data->base.dispatch_grf_start_reg = v8->payload().num_regs;
assert(v8->payload().num_regs % reg_unit(devinfo) == 0);
prog_data->base.dispatch_grf_start_reg = v8->payload().num_regs / reg_unit(devinfo);
prog_data->reg_blocks_8 = brw_register_blocks(v8->grf_used);
const performance &perf = v8->performance_analysis.require();
throughput = MAX2(throughput, perf.throughput);
@@ -7920,7 +7923,10 @@ brw_compile_fs(const struct brw_compiler *compiler,
v16->fail_msg);
} else {
simd16_cfg = v16->cfg;
prog_data->dispatch_grf_start_reg_16 = v16->payload().num_regs;
assert(v16->payload().num_regs % reg_unit(devinfo) == 0);
prog_data->dispatch_grf_start_reg_16 = v16->payload().num_regs / reg_unit(devinfo);
prog_data->reg_blocks_16 = brw_register_blocks(v16->grf_used);
const performance &perf = v16->performance_analysis.require();
throughput = MAX2(throughput, perf.throughput);
@@ -7954,7 +7960,10 @@ brw_compile_fs(const struct brw_compiler *compiler,
"SIMD32 shader inefficient\n");
} else {
simd32_cfg = v32->cfg;
prog_data->dispatch_grf_start_reg_32 = v32->payload().num_regs;
assert(v32->payload().num_regs % reg_unit(devinfo) == 0);
prog_data->dispatch_grf_start_reg_32 = v32->payload().num_regs / reg_unit(devinfo);
prog_data->reg_blocks_32 = brw_register_blocks(v32->grf_used);
throughput = MAX2(throughput, perf.throughput);
}

4
src/intel/compiler/brw_shader.cpp
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@@ -1396,7 +1396,9 @@ brw_compile_tes(const struct brw_compiler *compiler,
return NULL;
}
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs;
assert(v.payload().num_regs % reg_unit(devinfo) == 0);
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo);
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_generator g(compiler, &params->base,

5
src/intel/compiler/brw_vec4.cpp
View File

@@ -23,6 +23,7 @@
#include "brw_vec4.h"
#include "brw_fs.h"
#include "brw_eu.h"
#include "brw_cfg.h"
#include "brw_nir.h"
#include "brw_vec4_builder.h"
@@ -2643,7 +2644,9 @@ brw_compile_vs(const struct brw_compiler *compiler,
return NULL;
}
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs;
assert(v.payload().num_regs % reg_unit(compiler->devinfo) == 0);
prog_data->base.base.dispatch_grf_start_reg =
v.payload().num_regs / reg_unit(compiler->devinfo);
fs_generator g(compiler, &params->base,
&prog_data->base.base, v.runtime_check_aads_emit,

6
src/intel/compiler/brw_vec4_gs_visitor.cpp
View File

@@ -29,6 +29,7 @@
#include "brw_vec4_gs_visitor.h"
#include "gfx6_gs_visitor.h"
#include "brw_eu.h"
#include "brw_cfg.h"
#include "brw_fs.h"
#include "brw_nir.h"
@@ -822,7 +823,10 @@ brw_compile_gs(const struct brw_compiler *compiler,
params->base.stats != NULL, debug_enabled);
if (v.run_gs()) {
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs;
assert(v.payload().num_regs % reg_unit(compiler->devinfo) == 0);
prog_data->base.base.dispatch_grf_start_reg =
v.payload().num_regs / reg_unit(compiler->devinfo);
fs_generator g(compiler, &params->base,
&prog_data->base.base, false, MESA_SHADER_GEOMETRY);

3
src/intel/compiler/brw_vec4_tcs.cpp
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@@ -456,7 +456,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
return NULL;
}
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs;
assert(v.payload().num_regs % reg_unit(devinfo) == 0);
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo);
fs_generator g(compiler, &params->base,
&prog_data->base.base, false, MESA_SHADER_TESS_CTRL);

1
src/intel/compiler/brw_vec4_tcs.h
View File

@@ -31,6 +31,7 @@
#define BRW_VEC4_TCS_H
#include "brw_compiler.h"
#include "brw_eu.h"
#include "brw_vec4.h"
#ifdef __cplusplus