diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index aec9adad704..c833951ca3a 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1151,31 +1151,18 @@ static void
 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
                           struct radv_graphics_pipeline *pipeline)
 {
-   const struct radv_graphics_pipeline *old_pipeline = cmd_buffer->state.emitted_graphics_pipeline;
-
    if (pipeline->base.device->physical_device->rad_info.gfx_level < GFX9)
       return;
 
-   if (old_pipeline &&
-       old_pipeline->binning.pa_sc_binner_cntl_0 ==
-          pipeline->binning.pa_sc_binner_cntl_0)
+   if (pipeline->binning.pa_sc_binner_cntl_0 == cmd_buffer->state.last_pa_sc_binner_cntl_0)
       return;
 
-   bool binning_flush = false;
-   if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
-       cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
-       cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
-       cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) {
-      binning_flush = !old_pipeline ||
-                      G_028C44_BINNING_MODE(old_pipeline->binning.pa_sc_binner_cntl_0) !=
-                         G_028C44_BINNING_MODE(pipeline->binning.pa_sc_binner_cntl_0);
-   }
-
    radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
-                          pipeline->binning.pa_sc_binner_cntl_0 |
-                             S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
+                          pipeline->binning.pa_sc_binner_cntl_0);
 
    cmd_buffer->state.context_roll_without_scissor_emitted = true;
+
+   cmd_buffer->state.last_pa_sc_binner_cntl_0 = pipeline->binning.pa_sc_binner_cntl_0;
 }
 
 static void
@@ -4841,6 +4828,7 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi
    cmd_buffer->state.mesh_shading = false;
    cmd_buffer->state.last_vrs_rates = -1;
    cmd_buffer->state.last_vrs_rates_sgpr_idx = -1;
+   cmd_buffer->state.last_pa_sc_binner_cntl_0 = -1;
    cmd_buffer->usage_flags = pBeginInfo->flags;
 
    if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) {
@@ -6266,6 +6254,8 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
 
       primary->state.last_vrs_rates = secondary->state.last_vrs_rates;
       primary->state.last_vrs_rates_sgpr_idx = secondary->state.last_vrs_rates_sgpr_idx;
+
+      primary->state.last_pa_sc_binner_cntl_0 = secondary->state.last_pa_sc_binner_cntl_0;
    }
 
    /* After executing commands from secondary buffers we have to dirty
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 434543858b1..0de71148616 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4709,10 +4709,14 @@ radv_pipeline_init_disabled_binning_state(struct radv_graphics_pipeline *pipelin
          S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) | S_028C44_BIN_SIZE_X(0) |
          S_028C44_BIN_SIZE_Y(0) | S_028C44_BIN_SIZE_X_EXTEND(2) |       /* 128 */
          S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
-         S_028C44_DISABLE_START_OF_PRIM(1);
+         S_028C44_DISABLE_START_OF_PRIM(1) |
+         S_028C44_FLUSH_ON_BINNING_TRANSITION(1);
    } else {
       pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
-                            S_028C44_DISABLE_START_OF_PRIM(1);
+                            S_028C44_DISABLE_START_OF_PRIM(1) |
+                            S_028C44_FLUSH_ON_BINNING_TRANSITION(pdevice->rad_info.family == CHIP_VEGA12 ||
+                                                                 pdevice->rad_info.family == CHIP_VEGA20 ||
+                                                                 pdevice->rad_info.family >= CHIP_RAVEN2);
    }
 
    pipeline->binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
@@ -4746,7 +4750,11 @@ radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline,
          S_028C44_CONTEXT_STATES_PER_BIN(settings->context_states_per_bin - 1) |
          S_028C44_PERSISTENT_STATES_PER_BIN(settings->persistent_states_per_bin - 1) |
          S_028C44_DISABLE_START_OF_PRIM(1) |
-         S_028C44_FPOVS_PER_BATCH(settings->fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1);
+         S_028C44_FPOVS_PER_BATCH(settings->fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1) |
+         S_028C44_FLUSH_ON_BINNING_TRANSITION(device->physical_device->rad_info.family == CHIP_VEGA12 ||
+                                              device->physical_device->rad_info.family == CHIP_VEGA20 ||
+                                              device->physical_device->rad_info.family >= CHIP_RAVEN2);
+
 
       pipeline->binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
    } else
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 56efccf6255..517d702a501 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1615,6 +1615,9 @@ struct radv_cmd_state {
    /* Tessellation info when patch control points is dynamic. */
    unsigned tess_num_patches;
    unsigned tess_lds_size;
+
+   /* Binning state */
+   unsigned last_pa_sc_binner_cntl_0;
 };
 
 struct radv_cmd_buffer_upload {