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ac/surface: implement CmaskAddrFromCoord in NIR

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It's similar to DCC, only GFX9 is currently supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
This commit is contained in:
Samuel Pitoiset
2021-07-30 14:19:26 +02:00
committed by Marge Bot
parent eedc0b59b7
commit a49b397041
2 changed files with 94 additions and 55 deletions
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62
src/amd/common/ac_surface.c
View File

@@ -2956,24 +2956,17 @@ static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct
nir_ixor(b, nir_ushr(b, address, one), pipeXor));
}
nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
unsigned bpe, struct gfx9_meta_equation *equation,
nir_ssa_def *dcc_pitch, nir_ssa_def *dcc_height,
nir_ssa_def *dcc_slice_size,
static nir_ssa_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info,
struct gfx9_meta_equation *equation,
nir_ssa_def *meta_pitch, nir_ssa_def *meta_height,
nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
nir_ssa_def *sample, nir_ssa_def *pipe_xor)
nir_ssa_def *sample, nir_ssa_def *pipe_xor,
nir_ssa_def **bit_position)
{
nir_ssa_def *zero = nir_imm_int(b, 0);
nir_ssa_def *one = nir_imm_int(b, 1);
if (info->chip_class >= GFX10) {
unsigned bpp_log2 = util_logbase2(bpe);
return gfx10_nir_meta_addr_from_coord(b, info, equation, bpp_log2 - 8, 1,
dcc_pitch, dcc_slice_size,
x, y, z, pipe_xor);
} else {
assert(info->chip_class == GFX9);
assert(info->chip_class >= GFX9);
unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
@@ -2981,8 +2974,8 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info
unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
unsigned numPipeBits = equation->u.gfx9.num_pipe_bits;
nir_ssa_def *pitchInBlock = nir_ushr_imm(b, dcc_pitch, meta_block_width_log2);
nir_ssa_def *sliceSizeInBlock = nir_imul(b, nir_ushr_imm(b, dcc_height, meta_block_height_log2),
nir_ssa_def *pitchInBlock = nir_ushr_imm(b, meta_pitch, meta_block_width_log2);
nir_ssa_def *sliceSizeInBlock = nir_imul(b, nir_ushr_imm(b, meta_height, meta_block_height_log2),
pitchInBlock);
nir_ssa_def *xb = nir_ushr_imm(b, x, meta_block_width_log2);
@@ -3022,12 +3015,51 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info
equation->u.gfx9.bit[last].coord[0].ord),
nir_imm_int(b, last)));
if (bit_position)
*bit_position = nir_ishl(b, nir_iand(b, address, nir_imm_int(b, 1)),
nir_imm_int(b, 2));
nir_ssa_def *pipeXor = nir_iand_imm(b, pipe_xor, (1 << numPipeBits) - 1);
return nir_ixor(b, nir_ushr(b, address, one),
nir_ishl(b, pipeXor, nir_imm_int(b, m_pipeInterleaveLog2)));
}
nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
unsigned bpe, struct gfx9_meta_equation *equation,
nir_ssa_def *dcc_pitch, nir_ssa_def *dcc_height,
nir_ssa_def *dcc_slice_size,
nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
nir_ssa_def *sample, nir_ssa_def *pipe_xor)
{
if (info->chip_class >= GFX10) {
unsigned bpp_log2 = util_logbase2(bpe);
return gfx10_nir_meta_addr_from_coord(b, info, equation, bpp_log2 - 8, 1,
dcc_pitch, dcc_slice_size,
x, y, z, pipe_xor);
} else {
return gfx9_nir_meta_addr_from_coord(b, info, equation, dcc_pitch,
dcc_height, x, y, z,
sample, pipe_xor, NULL);
}
}
nir_ssa_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info,
struct gfx9_meta_equation *equation,
nir_ssa_def *cmask_pitch, nir_ssa_def *cmask_height,
nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
nir_ssa_def *pipe_xor,
nir_ssa_def **bit_position)
{
nir_ssa_def *zero = nir_imm_int(b, 0);
assert(info->chip_class == GFX9);
return gfx9_nir_meta_addr_from_coord(b, info, equation, cmask_pitch,
cmask_height, x, y, z, zero,
pipe_xor, bit_position);
}
nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info,
struct gfx9_meta_equation *equation,
nir_ssa_def *htile_pitch,

7
src/amd/common/ac_surface.h
View File

@@ -477,6 +477,13 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info
nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
nir_ssa_def *sample, nir_ssa_def *pipe_xor);
nir_ssa_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info,
struct gfx9_meta_equation *equation,
nir_ssa_def *cmask_pitch, nir_ssa_def *cmask_height,
nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
nir_ssa_def *pipe_xor,
nir_ssa_def **bit_position);
nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info,
struct gfx9_meta_equation *equation,
nir_ssa_def *htile_pitch,