ac/surface: implement CmaskAddrFromCoord in NIR
It's similar to DCC, only GFX9 is currently supported. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
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Samuel Pitoiset
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Marge Bot
Marge Bot
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eedc0b59b7
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a49b397041
@@ -2956,6 +2956,74 @@ static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct
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nir_ixor(b, nir_ushr(b, address, one), pipeXor));
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}
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static nir_ssa_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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struct gfx9_meta_equation *equation,
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nir_ssa_def *meta_pitch, nir_ssa_def *meta_height,
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nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
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nir_ssa_def *sample, nir_ssa_def *pipe_xor,
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nir_ssa_def **bit_position)
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{
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nir_ssa_def *zero = nir_imm_int(b, 0);
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nir_ssa_def *one = nir_imm_int(b, 1);
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assert(info->chip_class >= GFX9);
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unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
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unsigned meta_block_depth_log2 = util_logbase2(equation->meta_block_depth);
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unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
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unsigned numPipeBits = equation->u.gfx9.num_pipe_bits;
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nir_ssa_def *pitchInBlock = nir_ushr_imm(b, meta_pitch, meta_block_width_log2);
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nir_ssa_def *sliceSizeInBlock = nir_imul(b, nir_ushr_imm(b, meta_height, meta_block_height_log2),
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pitchInBlock);
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nir_ssa_def *xb = nir_ushr_imm(b, x, meta_block_width_log2);
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nir_ssa_def *yb = nir_ushr_imm(b, y, meta_block_height_log2);
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nir_ssa_def *zb = nir_ushr_imm(b, z, meta_block_depth_log2);
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nir_ssa_def *blockIndex = nir_iadd(b, nir_iadd(b, nir_imul(b, zb, sliceSizeInBlock),
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nir_imul(b, yb, pitchInBlock)), xb);
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nir_ssa_def *coords[] = {x, y, z, sample, blockIndex};
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nir_ssa_def *address = zero;
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unsigned num_bits = equation->u.gfx9.num_bits;
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assert(num_bits <= 32);
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/* Compute the address up until the last bit that doesn't use the block index. */
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for (unsigned i = 0; i < num_bits - 1; i++) {
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nir_ssa_def *xor = zero;
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for (unsigned c = 0; c < 5; c++) {
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if (equation->u.gfx9.bit[i].coord[c].dim >= 5)
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continue;
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assert(equation->u.gfx9.bit[i].coord[c].ord < 32);
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nir_ssa_def *ison =
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nir_iand(b, nir_ushr_imm(b, coords[equation->u.gfx9.bit[i].coord[c].dim],
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equation->u.gfx9.bit[i].coord[c].ord), one);
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xor = nir_ixor(b, xor, ison);
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}
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address = nir_ior(b, address, nir_ishl(b, xor, nir_imm_int(b, i)));
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}
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/* Fill the remaining bits with the block index. */
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unsigned last = num_bits - 1;
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address = nir_ior(b, address,
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nir_ishl(b, nir_ushr_imm(b, blockIndex,
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equation->u.gfx9.bit[last].coord[0].ord),
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nir_imm_int(b, last)));
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if (bit_position)
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*bit_position = nir_ishl(b, nir_iand(b, address, nir_imm_int(b, 1)),
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nir_imm_int(b, 2));
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nir_ssa_def *pipeXor = nir_iand_imm(b, pipe_xor, (1 << numPipeBits) - 1);
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return nir_ixor(b, nir_ushr(b, address, one),
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nir_ishl(b, pipeXor, nir_imm_int(b, m_pipeInterleaveLog2)));
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}
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nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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unsigned bpe, struct gfx9_meta_equation *equation,
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nir_ssa_def *dcc_pitch, nir_ssa_def *dcc_height,
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@@ -2963,9 +3031,6 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info
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nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
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nir_ssa_def *sample, nir_ssa_def *pipe_xor)
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{
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nir_ssa_def *zero = nir_imm_int(b, 0);
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nir_ssa_def *one = nir_imm_int(b, 1);
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if (info->chip_class >= GFX10) {
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unsigned bpp_log2 = util_logbase2(bpe);
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@@ -2973,61 +3038,28 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info
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dcc_pitch, dcc_slice_size,
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x, y, z, pipe_xor);
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} else {
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assert(info->chip_class == GFX9);
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unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
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unsigned meta_block_depth_log2 = util_logbase2(equation->meta_block_depth);
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unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
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unsigned numPipeBits = equation->u.gfx9.num_pipe_bits;
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nir_ssa_def *pitchInBlock = nir_ushr_imm(b, dcc_pitch, meta_block_width_log2);
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nir_ssa_def *sliceSizeInBlock = nir_imul(b, nir_ushr_imm(b, dcc_height, meta_block_height_log2),
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pitchInBlock);
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nir_ssa_def *xb = nir_ushr_imm(b, x, meta_block_width_log2);
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nir_ssa_def *yb = nir_ushr_imm(b, y, meta_block_height_log2);
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nir_ssa_def *zb = nir_ushr_imm(b, z, meta_block_depth_log2);
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nir_ssa_def *blockIndex = nir_iadd(b, nir_iadd(b, nir_imul(b, zb, sliceSizeInBlock),
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nir_imul(b, yb, pitchInBlock)), xb);
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nir_ssa_def *coords[] = {x, y, z, sample, blockIndex};
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nir_ssa_def *address = zero;
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unsigned num_bits = equation->u.gfx9.num_bits;
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assert(num_bits <= 32);
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/* Compute the address up until the last bit that doesn't use the block index. */
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for (unsigned i = 0; i < num_bits - 1; i++) {
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nir_ssa_def *xor = zero;
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for (unsigned c = 0; c < 5; c++) {
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if (equation->u.gfx9.bit[i].coord[c].dim >= 5)
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continue;
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assert(equation->u.gfx9.bit[i].coord[c].ord < 32);
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nir_ssa_def *ison =
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nir_iand(b, nir_ushr_imm(b, coords[equation->u.gfx9.bit[i].coord[c].dim],
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equation->u.gfx9.bit[i].coord[c].ord), one);
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xor = nir_ixor(b, xor, ison);
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}
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address = nir_ior(b, address, nir_ishl(b, xor, nir_imm_int(b, i)));
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}
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/* Fill the remaining bits with the block index. */
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unsigned last = num_bits - 1;
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address = nir_ior(b, address,
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nir_ishl(b, nir_ushr_imm(b, blockIndex,
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equation->u.gfx9.bit[last].coord[0].ord),
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nir_imm_int(b, last)));
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nir_ssa_def *pipeXor = nir_iand_imm(b, pipe_xor, (1 << numPipeBits) - 1);
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return nir_ixor(b, nir_ushr(b, address, one),
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nir_ishl(b, pipeXor, nir_imm_int(b, m_pipeInterleaveLog2)));
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return gfx9_nir_meta_addr_from_coord(b, info, equation, dcc_pitch,
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dcc_height, x, y, z,
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sample, pipe_xor, NULL);
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}
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}
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nir_ssa_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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struct gfx9_meta_equation *equation,
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nir_ssa_def *cmask_pitch, nir_ssa_def *cmask_height,
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nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
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nir_ssa_def *pipe_xor,
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nir_ssa_def **bit_position)
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{
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nir_ssa_def *zero = nir_imm_int(b, 0);
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assert(info->chip_class == GFX9);
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return gfx9_nir_meta_addr_from_coord(b, info, equation, cmask_pitch,
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cmask_height, x, y, z, zero,
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pipe_xor, bit_position);
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}
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nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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struct gfx9_meta_equation *equation,
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nir_ssa_def *htile_pitch,
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@@ -477,6 +477,13 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info
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nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
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nir_ssa_def *sample, nir_ssa_def *pipe_xor);
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nir_ssa_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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struct gfx9_meta_equation *equation,
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nir_ssa_def *cmask_pitch, nir_ssa_def *cmask_height,
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nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,
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nir_ssa_def *pipe_xor,
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nir_ssa_def **bit_position);
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nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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struct gfx9_meta_equation *equation,
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nir_ssa_def *htile_pitch,
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