intel: Make gen12 URB space reservation dependent on compute engine presence

Tigerlake PRM: Volume 2c: Command Reference: Registers Part 2 - Registers M through Z
RCU_MODE :: Compute Engine Enable

   This bit indicates if Compute Engine (a.k.a Dual Context or Multi
   Context) is enabled or not. This bit must be treated as global
   control for enabling and disabling of compute engine. Hardware
   allocates required resources for the compute engine based on this
   bit.
   ....
   HW reserves 4KB of URB space...

Right now no gen12 platform has Dual Context enabled in kernel side,
exposing a compute engine but that can change, so here adding
has_compute_engine to intel_device_info and only reserving URB space
if compute engine is available.

While at it also fixing the error path when pb_slabs_init() fails.

Bspec: 46034
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031>

src/gallium/drivers/iris/iris_bufmgr.c

@@ -2411,6 +2411,14 @@ iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
    bufmgr->bo_reuse = bo_reuse;
    iris_bufmgr_get_meminfo(bufmgr, devinfo);
 
+   struct intel_query_engine_info *engine_info;
+   engine_info = intel_engine_get_info(bufmgr->fd, bufmgr->devinfo.kmd_type);
+   if (!engine_info)
+      goto error_engine_info;
+   bufmgr->devinfo.has_compute_engine = intel_engines_count(engine_info,
+                                                            INTEL_ENGINE_CLASS_COMPUTE);
+   free(engine_info);
+
    STATIC_ASSERT(IRIS_MEMZONE_SHADER_START == 0ull);
    const uint64_t _4GB = 1ull << 32;
    const uint64_t _2GB = 1ul << 31;
@@ -2471,8 +2479,7 @@ iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
                          iris_can_reclaim_slab,
                          iris_slab_alloc,
                          (void *) iris_slab_free)) {
-         free(bufmgr);
-         return NULL;
+         goto error_slabs_init;
       }
       min_slab_order = max_order + 1;
    }
@@ -2495,6 +2502,18 @@ iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
    iris_init_border_color_pool(bufmgr, &bufmgr->border_color_pool);
 
    return bufmgr;
+
+error_slabs_init:
+   for (unsigned i = 0; i < NUM_SLAB_ALLOCATORS; i++) {
+      if (!bufmgr->bo_slabs[i].groups)
+         break;
+
+      pb_slabs_deinit(&bufmgr->bo_slabs[i]);
+   }
+error_engine_info:
+   close(bufmgr->fd);
+   free(bufmgr);
+   return NULL;
 }
 
 static struct iris_bufmgr *

src/intel/common/intel_urb_config.c

@@ -85,7 +85,7 @@ intel_get_urb_config(const struct intel_device_info *devinfo,
     *    only 124KB (per bank). More detailed description available in "L3
     *    Cache" section of the B-Spec."
     */
-   if (devinfo->verx10 == 120) {
+   if (devinfo->verx10 == 120 && devinfo->has_compute_engine) {
       assert(devinfo->num_slices == 1);
       urb_size_kB -= 4 * devinfo->l3_banks;
    }

src/intel/dev/intel_device_info.h

@@ -178,6 +178,11 @@ struct intel_device_info
     */
    bool has_coarse_pixel_primitive_and_cb;
 
+   /**
+    * Whether this platform has compute engine
+    */
+   bool has_compute_engine;
+
    /**
     * Some versions of Gen hardware don't do centroid interpolation correctly
     * on unlit pixels, causing incorrect values for derivatives near triangle

src/intel/vulkan/anv_device.c

@@ -975,6 +975,8 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
    device->master_fd = master_fd;
 
    device->engine_info = intel_engine_get_info(fd, device->info.kmd_type);
+   device->info.has_compute_engine = intel_engines_count(device->engine_info,
+                                                         INTEL_ENGINE_CLASS_COMPUTE);
    anv_physical_device_init_queue_families(device);
 
    anv_physical_device_init_perf(device, fd);