intel/fs: optimize uniform SSBO & shared loads

Using divergence analysis, figure out when SSBO & shared memory loads
are uniform and carry the data only once in register space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

src/intel/compiler/brw_nir.h

@@ -187,6 +187,9 @@ bool brw_nir_opt_peephole_imul32x16(nir_shader *shader);
 bool brw_nir_clamp_per_vertex_loads(nir_shader *shader,
                                     unsigned input_vertices);
 
+bool brw_nir_blockify_uniform_loads(nir_shader *shader,
+                                    const struct intel_device_info *devinfo);
+
 void brw_nir_optimize(nir_shader *nir,
                       const struct brw_compiler *compiler,
                       bool is_scalar);