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pan/midgard: Handle misc. cppcheck warnings

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Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig
2019-12-13 10:13:24 -05:00
parent f204791cd6
commit a337bf319c
5 changed files with 13 additions and 15 deletions
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12
src/panfrost/midgard/disassemble.c
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@@ -487,10 +487,8 @@ print_mask(uint8_t mask, unsigned bits, midgard_dest_override override)
const char *alphabet = components; const char *alphabet = components;
if (override == midgard_dest_override_upper) { if (override == midgard_dest_override_upper)
unsigned components = 128 / bits; alphabet += (128 / bits);
alphabet += components;
}
for (unsigned i = 0; i < 8; i += skip) { for (unsigned i = 0; i < 8; i += skip) {
bool a = (mask & (1 << i)) != 0; bool a = (mask & (1 << i)) != 0;
@@ -1310,7 +1308,7 @@ print_texture_word(uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned
/* Output modifiers are always interpreted floatly */ /* Output modifiers are always interpreted floatly */
print_outmod(texture->outmod, false); print_outmod(texture->outmod, false);
printf(" %sr%d", texture->out_full ? "" : "h", printf(" %sr%u", texture->out_full ? "" : "h",
out_reg_base + texture->out_reg_select); out_reg_base + texture->out_reg_select);
print_mask_4(texture->mask, texture->out_upper); print_mask_4(texture->mask, texture->out_upper);
assert(!(texture->out_full && texture->out_upper)); assert(!(texture->out_full && texture->out_upper));
@@ -1346,7 +1344,7 @@ print_texture_word(uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned
} }
print_swizzle_vec4(texture->swizzle, false, false); print_swizzle_vec4(texture->swizzle, false, false);
printf(", %sr%d", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select); printf(", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
assert(!(texture->in_reg_full && texture->in_reg_upper)); assert(!(texture->in_reg_full && texture->in_reg_upper));
/* TODO: integrate with swizzle */ /* TODO: integrate with swizzle */
@@ -1372,7 +1370,7 @@ print_texture_word(uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned
bool select = texture->offset_x & 2; bool select = texture->offset_x & 2;
bool upper = texture->offset_x & 4; bool upper = texture->offset_x & 4;
printf("%sr%d", full ? "" : "h", in_reg_base + select); printf("%sr%u", full ? "" : "h", in_reg_base + select);
assert(!(texture->out_full && texture->out_upper)); assert(!(texture->out_full && texture->out_upper));
/* TODO: integrate with swizzle */ /* TODO: integrate with swizzle */

2
src/panfrost/midgard/midgard_emit.c
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@@ -142,7 +142,7 @@ mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
for (unsigned i = 0; i < 2; ++i) { for (unsigned i = 0; i < 2; ++i) {
assert(swizzle[i] <= max_component); assert(swizzle[i] <= max_component);
unsigned a = swizzle[i] & 1 ? unsigned a = (swizzle[i] & 1) ?
(COMPONENT_W << 2) | COMPONENT_Z : (COMPONENT_W << 2) | COMPONENT_Z :
(COMPONENT_Y << 2) | COMPONENT_X; (COMPONENT_Y << 2) | COMPONENT_X;

8
src/panfrost/midgard/midgard_ra_pipeline.c
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@@ -56,8 +56,8 @@ mir_pipeline_ins(
/* Analyze the bundle for a per-byte read mask */ /* Analyze the bundle for a per-byte read mask */
for (unsigned i = 0; i < bundle->instruction_count; ++i) { for (unsigned j = 0; j < bundle->instruction_count; ++j) {
midgard_instruction *q = bundle->instructions[i]; midgard_instruction *q = bundle->instructions[j];
read_mask |= mir_bytemask_of_read_components(q, node); read_mask |= mir_bytemask_of_read_components(q, node);
/* The fragment colour can't be pipelined (well, it is /* The fragment colour can't be pipelined (well, it is
@@ -69,8 +69,8 @@ mir_pipeline_ins(
} }
/* Now analyze for a write mask */ /* Now analyze for a write mask */
for (unsigned i = 0; i < bundle->instruction_count; ++i) { for (unsigned j = 0; j < bundle->instruction_count; ++j) {
midgard_instruction *q = bundle->instructions[i]; midgard_instruction *q = bundle->instructions[j];
if (q->dest != node) continue; if (q->dest != node) continue;
/* Remove the written mask from the read requirements */ /* Remove the written mask from the read requirements */

2
src/panfrost/midgard/midgard_schedule.c
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@@ -914,12 +914,12 @@ mir_schedule_alu(
mir_choose_alu(&sadd, instructions, worklist, len, &predicate, UNIT_SADD); mir_choose_alu(&sadd, instructions, worklist, len, &predicate, UNIT_SADD);
/* Check if writeout reads its own register */ /* Check if writeout reads its own register */
bool bad_writeout = false;
if (branch && branch->writeout) { if (branch && branch->writeout) {
midgard_instruction *stages[] = { sadd, vadd, smul }; midgard_instruction *stages[] = { sadd, vadd, smul };
unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0];
unsigned writeout_mask = 0x0; unsigned writeout_mask = 0x0;
bool bad_writeout = false;
for (unsigned i = 0; i < ARRAY_SIZE(stages); ++i) { for (unsigned i = 0; i < ARRAY_SIZE(stages); ++i) {
if (!stages[i]) if (!stages[i])

4
src/panfrost/midgard/mir.c
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@@ -312,7 +312,7 @@ mir_to_bytemask(midgard_reg_mode mode, unsigned mask)
case midgard_reg_mode_16: { case midgard_reg_mode_16: {
unsigned space = unsigned space =
((mask & 0x1) << (0 - 0)) | (mask & 0x1) |
((mask & 0x2) << (2 - 1)) | ((mask & 0x2) << (2 - 1)) |
((mask & 0x4) << (4 - 2)) | ((mask & 0x4) << (4 - 2)) |
((mask & 0x8) << (6 - 3)) | ((mask & 0x8) << (6 - 3)) |
@@ -326,7 +326,7 @@ mir_to_bytemask(midgard_reg_mode mode, unsigned mask)
case midgard_reg_mode_32: { case midgard_reg_mode_32: {
unsigned space = unsigned space =
((mask & 0x1) << (0 - 0)) | (mask & 0x1) |
((mask & 0x2) << (4 - 1)) | ((mask & 0x2) << (4 - 1)) |
((mask & 0x4) << (8 - 2)) | ((mask & 0x4) << (8 - 2)) |
((mask & 0x8) << (12 - 3)); ((mask & 0x8) << (12 - 3));