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Revert "intel/fs: Use a pure vertical stride for large register strides"

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This reverts commit e8c9e65185.

With the actual bug fixed (by commit 6ac2d16901), this is not
necessary. I'm doubtful of its correctness in any case.
This commit is contained in:
Matt Turner
2017-11-14 11:24:08 -08:00
parent 6ac2d16901
commit a31d038208
1 changed files with 3 additions and 13 deletions
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16
src/intel/compiler/brw_fs_generator.cpp
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@@ -90,19 +90,9 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
* different execution size when the number of components * different execution size when the number of components
* written to each destination GRF is not the same. * written to each destination GRF is not the same.
*/ */
if (reg->stride > 4) { const unsigned width = MIN2(reg_width, phys_width);
/* For registers with an exceptionally large stride, we use a brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
* width of 1 and only use the vertical stride. This only works brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
* for sources since destinations require hstride == 1.
*/
assert(reg != &inst->dst);
brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, reg->stride, 1, 0);
} else {
const unsigned width = MIN2(reg_width, phys_width);
brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
}
if (devinfo->gen == 7 && !devinfo->is_haswell) { if (devinfo->gen == 7 && !devinfo->is_haswell) {
/* From the IvyBridge PRM (EU Changes by Processor Generation, page 13): /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):