diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index 96eb12b7816..ec5253f959b 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -1706,7 +1706,7 @@ agx_emit_jump(agx_builder *b, nir_jump_instr *instr)
    }
 
    /* Update the counter and flush */
-   agx_nest(b, agx_immediate(nestings));
+   agx_nest(b, nestings);
 
    /* Jumps must come at the end of a block */
    agx_emit_logical_end(b);
@@ -1960,7 +1960,7 @@ emit_first_cf(agx_context *ctx)
       return;
 
    agx_builder _b = agx_init_builder(ctx, agx_after_block(ctx->current_block));
-   agx_nest(&_b, agx_immediate(0));
+   agx_nest(&_b, 0);
    ctx->any_cf = true;
 }
 
diff --git a/src/asahi/compiler/agx_opcodes.py b/src/asahi/compiler/agx_opcodes.py
index 78bd18b732b..ae2cd34ae32 100644
--- a/src/asahi/compiler/agx_opcodes.py
+++ b/src/asahi/compiler/agx_opcodes.py
@@ -403,5 +403,5 @@ op("unit_test", _, dests = 0, srcs = 1, can_eliminate = False)
 # to be coalesced during RA, rather than lowered to a real move. 
 op("preload", _, srcs = 1)
 
-# Set the nesting counter. Lowers to mov r0l, x after RA.
-op("nest", _, dests = 0, srcs = 1, can_eliminate = False)
+# Set the nesting counter. Lowers to mov_imm r0l, #nest after RA.
+op("nest", _, dests = 0, imms = [IMM], can_eliminate = False)
diff --git a/src/asahi/compiler/agx_register_allocate.c b/src/asahi/compiler/agx_register_allocate.c
index 1fea6f7519f..f3a0a56c89b 100644
--- a/src/asahi/compiler/agx_register_allocate.c
+++ b/src/asahi/compiler/agx_register_allocate.c
@@ -1243,7 +1243,7 @@ agx_ra(agx_context *ctx)
       /* Writes to the nesting counter lowered to the real register */
       case AGX_OPCODE_NEST: {
          agx_builder b = agx_init_builder(ctx, agx_before_instr(I));
-         agx_mov_to(&b, agx_register(0, AGX_SIZE_16), I->src[0]);
+         agx_mov_imm_to(&b, agx_register(0, AGX_SIZE_16), I->imm);
          agx_remove_instruction(I);
          break;
       }