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ac/gpu_info: add has_read_registers_query

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2018-05-02 20:01:39 -04:00
parent 9b1fdfc541
commit a2e9d9b4c1
4 changed files with 6 additions and 3 deletions
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2
src/amd/common/ac_gpu_info.c
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@@ -338,6 +338,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->chip_class >= CIK && info->chip_class <= VI && info->chip_class >= CIK && info->chip_class <= VI &&
info->drm_minor >= 13; info->drm_minor >= 13;
info->has_2d_tiling = true; info->has_2d_tiling = true;
info->has_read_registers_query = true;
info->num_render_backends = amdinfo->rb_pipes; info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */ /* The value returned by the kernel driver was wrong. */
@@ -498,6 +499,7 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads); printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings); printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
printf(" has_2d_tiling = %u\n", info->has_2d_tiling); printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
printf("Shader core info:\n"); printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock); printf(" max_shader_clock = %i\n", info->max_shader_clock);

1
src/amd/common/ac_gpu_info.h
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@@ -109,6 +109,7 @@ struct radeon_info {
bool has_unaligned_shader_loads; bool has_unaligned_shader_loads;
bool has_sparse_vm_mappings; bool has_sparse_vm_mappings;
bool has_2d_tiling; bool has_2d_tiling;
bool has_read_registers_query;
/* Shader cores. */ /* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */ uint32_t r600_max_quad_pipes; /* wave size / 16 */

5
src/gallium/drivers/radeonsi/si_debug.c
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@@ -294,9 +294,8 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
static void si_dump_debug_registers(struct si_context *sctx, FILE *f) static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
{ {
if (sctx->screen->info.drm_major == 2 && if (!sctx->screen->info.has_read_registers_query)
sctx->screen->info.drm_minor < 42) return;
return; /* no radeon support */
fprintf(f, "Memory-mapped registers:\n"); fprintf(f, "Memory-mapped registers:\n");
si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS); si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);

1
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
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@@ -550,6 +550,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.has_sparse_vm_mappings = false; ws->info.has_sparse_vm_mappings = false;
/* 2D tiling on CIK is supported since DRM 2.35.0 */ /* 2D tiling on CIK is supported since DRM 2.35.0 */
ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35; ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;