intel/fs: Add need_dest parameter to fs_visitor::nir_emit_alu
This is the same as the need_dest parameter to prepare_alu_destination_and_sources. This allows us to not change the register that is expected to hold an result if an instruction is re-emitted. This is particularly a problem if the re-emitted instruction is a partial write. A later patch will use this feature. No shader-db changes on any Intel platform. v2: Don't do the Boolean resolve when there is no destination. If the ALU instruction didn't write a register, there's nothing to resolve. This replaces an earlier patch "intel/fs: Allocate dummy destination register when need_dest is false". Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
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@@ -206,7 +206,8 @@ public:
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void nir_emit_loop(nir_loop *loop);
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void nir_emit_block(nir_block *block);
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void nir_emit_instr(nir_instr *instr);
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void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
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void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr,
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bool need_dest);
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bool try_emit_b2fi_of_inot(const brw::fs_builder &bld, fs_reg result,
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nir_alu_instr *instr);
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void nir_emit_load_const(const brw::fs_builder &bld,
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@@ -450,7 +450,7 @@ fs_visitor::nir_emit_instr(nir_instr *instr)
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switch (instr->type) {
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case nir_instr_type_alu:
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nir_emit_alu(abld, nir_instr_as_alu(instr));
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nir_emit_alu(abld, nir_instr_as_alu(instr), true);
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break;
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case nir_instr_type_deref:
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@@ -981,13 +981,14 @@ can_fuse_fmul_fsign(nir_alu_instr *instr, unsigned fsign_src)
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}
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void
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fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
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fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
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bool need_dest)
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{
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struct brw_wm_prog_key *fs_key = (struct brw_wm_prog_key *) this->key;
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fs_inst *inst;
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fs_reg op[4];
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fs_reg result = prepare_alu_destination_and_sources(bld, instr, op, true);
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fs_reg result = prepare_alu_destination_and_sources(bld, instr, op, need_dest);
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switch (instr->op) {
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case nir_op_mov:
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@@ -1836,6 +1837,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
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* to sign extend the low bit to 0/~0
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*/
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if (devinfo->gen <= 5 &&
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!result.is_null() &&
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(instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
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fs_reg masked = vgrf(glsl_type::int_type);
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bld.AND(masked, result, brw_imm_d(1));
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