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nir: fix nir_ishl_imm

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Both GLSL & SPIRV have undefined values for shift > bitsize. But SM5
says :

   "This instruction performs a component-wise shift of each 32-bit
    value in src0 left by an unsigned integer bit count provided by
    the LSB 5 bits (0-31 range) in src1, inserting 0."

Better to not hard code the wrong behavior in NIR.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e227bb9fd5 ("nir/builder: add ishl_imm helper")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@colllabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21720>
This commit is contained in:
Lionel Landwerlin
2023-03-05 23:12:36 +02:00
committed by Marge Bot
parent 5ec80ab37c
commit a278eeb719
1 changed files with 1 additions and 2 deletions
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3
src/compiler/nir/nir_builder.h
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@@ -841,9 +841,8 @@ nir_ishl_imm(nir_builder *build, nir_ssa_def *x, uint32_t y)
{ {
if (y == 0) { if (y == 0) {
return x; return x;
} else if (y >= x->bit_size) {
return nir_imm_intN_t(build, 0, x->bit_size);
} else { } else {
assert (y < x->bit_size);
return nir_ishl(build, x, nir_imm_int(build, y)); return nir_ishl(build, x, nir_imm_int(build, y));
} }
} }