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radv: set LDS TCS size at shaders creation for GFX9+

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5837>
This commit is contained in:
Samuel Pitoiset
2020-07-09 10:33:16 +02:00
committed by Marge Bot
parent cf89bdb9ba
commit a1b237b9ef
2 changed files with 5 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/amd/vulkan/radv_pipeline.c
View File

@@ -4054,20 +4054,11 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
static void static void
radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline, struct radv_pipeline *pipeline,
struct radv_shader_variant *shader, struct radv_shader_variant *shader)
const struct radv_tessellation_state *tess)
{ {
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
unsigned hs_rsrc2 = shader->config.rsrc2;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->num_lds_blocks);
} else {
hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->num_lds_blocks);
}
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2); radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
radeon_emit(cs, va >> 8); radeon_emit(cs, va >> 8);
@@ -4080,7 +4071,7 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2); radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
radeon_emit(cs, shader->config.rsrc1); radeon_emit(cs, shader->config.rsrc1);
radeon_emit(cs, hs_rsrc2); radeon_emit(cs, shader->config.rsrc2);
} else { } else {
radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4); radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
radeon_emit(cs, va >> 8); radeon_emit(cs, va >> 8);
@@ -4136,7 +4127,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes); radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
} }
radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess); radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM, radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
tess->tf_param); tess->tf_param);

2
src/amd/vulkan/radv_shader.c
View File

@@ -813,8 +813,10 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice,
*/ */
if (pdevice->rad_info.chip_class >= GFX10) { if (pdevice->rad_info.chip_class >= GFX10) {
vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1; vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
} else { } else {
vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1; vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
} }
} else { } else {
config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1); config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);