diff --git a/src/gallium/drivers/iris/iris_draw.c b/src/gallium/drivers/iris/iris_draw.c
index 00d672ffec4..2bf23ab1b3e 100644
--- a/src/gallium/drivers/iris/iris_draw.c
+++ b/src/gallium/drivers/iris/iris_draw.c
@@ -87,8 +87,8 @@ iris_update_draw_info(struct iris_context *ice,
       ice->state.vertices_per_patch = ice->state.patch_vertices;
       ice->state.dirty |= IRIS_DIRTY_VF_TOPOLOGY;
 
-      /* 8_PATCH TCS needs this for key->input_vertices */
-      if (compiler->use_tcs_8_patch)
+      /* MULTI_PATCH TCS needs this for key->input_vertices */
+      if (compiler->use_tcs_multi_patch)
          ice->state.stage_dirty |= IRIS_STAGE_DIRTY_UNCOMPILED_TCS;
 
       /* Flag constants dirty for gl_PatchVerticesIn if needed. */
diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c
index f4898ae897f..d2ab571ae6a 100644
--- a/src/gallium/drivers/iris/iris_program.c
+++ b/src/gallium/drivers/iris/iris_program.c
@@ -1611,7 +1611,7 @@ iris_update_compiled_tcs(struct iris_context *ice)
       .vue.base.program_string_id = tcs ? tcs->program_id : 0,
       ._tes_primitive_mode = tes_info->tess._primitive_mode,
       .input_vertices =
-         !tcs || compiler->use_tcs_8_patch ? ice->state.vertices_per_patch : 0,
+         !tcs || compiler->use_tcs_multi_patch ? ice->state.vertices_per_patch : 0,
       .quads_workaround = devinfo->ver < 9 &&
                           tes_info->tess._primitive_mode == TESS_PRIMITIVE_QUADS &&
                           tes_info->tess.spacing == TESS_SPACING_EQUAL,
@@ -2620,12 +2620,12 @@ iris_create_shader_state(struct pipe_context *ctx,
          .patch_outputs_written = info->patch_outputs_written,
       };
 
-      /* 8_PATCH mode needs the key to contain the input patch dimensionality.
+      /* MULTI_PATCH mode needs the key to contain the input patch dimensionality.
        * We don't have that information, so we randomly guess that the input
        * and output patches are the same size.  This is a bad guess, but we
        * can't do much better.
        */
-      if (screen->compiler->use_tcs_8_patch)
+      if (screen->compiler->use_tcs_multi_patch)
          key.tcs.input_vertices = info->tess.tcs_vertices_out;
 
       key_size = sizeof(key.tcs);
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index a2988c21c59..5eca00aa6a2 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -116,7 +116,7 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
 
    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 
-   compiler->use_tcs_8_patch = devinfo->ver >= 12;
+   compiler->use_tcs_multi_patch = devinfo->ver >= 12;
 
    /* Default to the sampler since that's what we've done since forever */
    compiler->indirect_ubos_use_sampler = true;
@@ -198,8 +198,8 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
          brw_nir_no_indirect_mask(compiler, i);
       nir_options->force_indirect_unrolling_sampler = devinfo->ver < 7;
 
-      if (compiler->use_tcs_8_patch) {
-         /* TCS 8_PATCH mode has multiple patches per subgroup */
+      if (compiler->use_tcs_multi_patch) {
+         /* TCS MULTI_PATCH mode has multiple patches per subgroup */
          nir_options->divergence_analysis_options &=
             ~nir_divergence_single_patch_per_tcs_subgroup;
       }
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 42385df0d9e..b9d79ad0c06 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -84,7 +84,7 @@ struct brw_compiler {
    void (*shader_perf_log)(void *, unsigned *id, const char *str, ...) PRINTFLIKE(3, 4);
 
    bool scalar_stage[MESA_ALL_SHADER_STAGES];
-   bool use_tcs_8_patch;
+   bool use_tcs_multi_patch;
    struct nir_shader_compiler_options *nir_options[MESA_ALL_SHADER_STAGES];
 
    /**
@@ -1258,7 +1258,7 @@ enum shader_dispatch_mode {
    DISPATCH_MODE_SIMD8 = 3,
 
    DISPATCH_MODE_TCS_SINGLE_PATCH = 0,
-   DISPATCH_MODE_TCS_8_PATCH = 2,
+   DISPATCH_MODE_TCS_MULTI_PATCH = 2,
 };
 
 /**
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 9372fd1bf52..fd2dec26348 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6674,7 +6674,7 @@ fs_visitor::set_tcs_invocation_id()
 
    invocation_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
 
-   if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH) {
+   if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH) {
       /* gl_InvocationID is just the thread number */
       bld.SHR(invocation_id, t, brw_imm_ud(instance_id_shift));
       return;
@@ -6706,13 +6706,13 @@ fs_visitor::run_tcs()
    struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key;
 
    assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH ||
-          vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH);
+          vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
 
    if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
       /* r1-r4 contain the ICP handles. */
       payload.num_regs = 5;
    } else {
-      assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH);
+      assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
       assert(tcs_key->input_vertices > 0);
       /* r1 contains output handles, r2 may contain primitive ID, then the
        * ICP handles occupy the next 1-32 registers.
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index bab2976aaf7..cae6e15eb73 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -297,7 +297,7 @@ public:
    fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
    fs_reg get_tcs_single_patch_icp_handle(const brw::fs_builder &bld,
                                           nir_intrinsic_instr *instr);
-   fs_reg get_tcs_eight_patch_icp_handle(const brw::fs_builder &bld,
+   fs_reg get_tcs_multi_patch_icp_handle(const brw::fs_builder &bld,
                                          nir_intrinsic_instr *instr);
    struct brw_reg get_tcs_output_urb_handle();
 
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index c810c571aaf..c040ed8004b 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2757,7 +2757,7 @@ fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder &bld,
 }
 
 fs_reg
-fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder &bld,
+fs_visitor::get_tcs_multi_patch_icp_handle(const fs_builder &bld,
                                            nir_intrinsic_instr *instr)
 {
    struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key;
@@ -2818,7 +2818,7 @@ fs_visitor::get_tcs_output_urb_handle()
    if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
       return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD);
    } else {
-      assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH);
+      assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
       return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
    }
 }
@@ -2832,8 +2832,8 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
    struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
    struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
 
-   bool eight_patch =
-      vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH;
+   bool multi_patch =
+      vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH;
 
    fs_reg dst;
    if (nir_intrinsic_infos[instr->intrinsic].has_dest)
@@ -2841,7 +2841,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
 
    switch (instr->intrinsic) {
    case nir_intrinsic_load_primitive_id:
-      bld.MOV(dst, fs_reg(eight_patch ? brw_vec8_grf(2, 0)
+      bld.MOV(dst, fs_reg(multi_patch ? brw_vec8_grf(2, 0)
                                       : brw_vec1_grf(0, 1)));
       break;
    case nir_intrinsic_load_invocation_id:
@@ -2906,7 +2906,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
       fs_inst *inst;
 
       fs_reg icp_handle =
-         eight_patch ? get_tcs_eight_patch_icp_handle(bld, instr)
+         multi_patch ? get_tcs_multi_patch_icp_handle(bld, instr)
                      : get_tcs_single_patch_icp_handle(bld, instr);
 
       /* We can only read two double components with each URB read, so
diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp
index 7747b209cb2..e4a5d1e66bc 100644
--- a/src/intel/compiler/brw_vec4_tcs.cpp
+++ b/src/intel/compiler/brw_vec4_tcs.cpp
@@ -320,7 +320,7 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 }
 
 /**
- * Return the number of patches to accumulate before an 8_PATCH mode thread is
+ * Return the number of patches to accumulate before a MULTI_PATCH mode thread is
  * launched.  In cases with a large number of input control points and a large
  * amount of VS outputs, the VS URB space needed to store an entire 8 patches
  * worth of data can be prohibitive, so it can be beneficial to launch threads
@@ -394,8 +394,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
 
    prog_data->patch_count_threshold = brw::get_patch_count_threshold(key->input_vertices);
 
-   if (compiler->use_tcs_8_patch) {
-      vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH;
+   if (compiler->use_tcs_multi_patch) {
+      vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_MULTI_PATCH;
       prog_data->instances = nir->info.tess.tcs_vertices_out;
       prog_data->include_primitive_id = has_primitive_id;
    } else {