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r600g: move MULTIWRITE setup into cb_misc_state for r6xx-r7xx

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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák
2012-07-07 07:40:36 +02:00
parent 0ea76916e6
commit a1a1ff5ec0
4 changed files with 20 additions and 21 deletions
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1
src/gallium/drivers/r600/r600_hw_context.c
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@@ -358,7 +358,6 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_0287A0_CB_SHADER_CONTROL, 0, 0},
{R_028800_DB_DEPTH_CONTROL, 0, 0},
{R_028804_CB_BLEND_CONTROL, 0, 0},
{R_028808_CB_COLOR_CONTROL, 0, 0},
{R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
{R_028000_DB_DEPTH_SIZE, 0, 0},

3
src/gallium/drivers/r600/r600_pipe.h
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@@ -84,8 +84,10 @@ struct r600_db_misc_state {
struct r600_cb_misc_state {
struct r600_atom atom;
unsigned cb_color_control; /* this comes from blend state */
unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
unsigned nr_cbufs;
bool multiwrite;
};
enum r600_pipe_state_id {
@@ -291,7 +293,6 @@ struct r600_context {
unsigned sx_alpha_test_control;
unsigned cb_shader_mask;
unsigned db_shader_control;
unsigned cb_color_control;
unsigned pa_sc_line_stipple;
unsigned pa_cl_clip_cntl;
/* for saving when using blitter */

4
src/gallium/drivers/r600/r600_state.c
View File

@@ -1703,9 +1703,13 @@ static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom
struct radeon_winsys_cs *cs = rctx->cs;
struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
r600_write_context_reg(cs, R_028238_CB_TARGET_MASK,
a->blend_colormask & fb_colormask);
r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
a->cb_color_control |
S_028808_MULTIWRITE_ENABLE(multiwrite));
}
static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)

33
src/gallium/drivers/r600/r600_state_common.c
View File

@@ -157,9 +157,6 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state)
return;
rstate = &blend->rstate;
rctx->states[rstate->id] = rstate;
/* Replace every bit except MULTIWRITE_ENABLE. */
rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
rctx->dual_src_blend = blend->dual_src_blend;
r600_context_pipe_state_set(rctx, rstate);
@@ -167,6 +164,11 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state)
rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
if (rctx->chip_class <= R700 &&
rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
}
void r600_set_blend_color(struct pipe_context *ctx,
@@ -563,9 +565,16 @@ void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
if (rctx->chip_class <= R700) {
bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
if (rctx->chip_class < EVERGREEN && rctx->vs_shader) {
r600_adjust_gprs(rctx);
if (rctx->cb_misc_state.multiwrite != multiwrite) {
rctx->cb_misc_state.multiwrite = multiwrite;
r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
if (rctx->vs_shader)
r600_adjust_gprs(rctx);
}
}
@@ -906,13 +915,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
if (rctx->chip_class <= R700) {
unsigned multi_write = !!rctx->ps_shader->current->shader.fs_write_all &&
(rctx->nr_cbufs > 1);
rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(multi_write);
r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
}
r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
}
@@ -932,13 +934,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
else if (prim == V_008958_DI_PT_LINESTRIP)
ls_mask = 2;
r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
if (rctx->chip_class <= R700) {
unsigned multi_write = !!rctx->ps_shader->current->shader.fs_write_all &&
(rctx->nr_cbufs > 1);
rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(multi_write);
r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
}
r600_pipe_state_mod_reg(&rctx->vgt,
rctx->vs_shader->current->pa_cl_vs_out_cntl |
(rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));