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intel: drop unused is_scalar function parameter in brw_nir_apply_key

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Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23098>
This commit is contained in:
Rohan Garg
2023-05-17 17:09:06 +02:00
parent 212810ac8a
commit a15cc833f9
8 changed files with 11 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/intel/compiler/brw_fs.cpp
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@@ -7463,7 +7463,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
const struct intel_device_info *devinfo = compiler->devinfo;
const unsigned max_subgroup_size = compiler->devinfo->ver >= 6 ? 32 : 16;
brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size, true);
brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size);
brw_nir_lower_fs_inputs(nir, devinfo, key);
brw_nir_lower_fs_outputs(nir);
@@ -7841,7 +7841,7 @@ brw_compile_cs(const struct brw_compiler *compiler,
nir_shader *shader = nir_shader_clone(mem_ctx, nir);
brw_nir_apply_key(shader, compiler, &key->base,
dispatch_width, true /* is_scalar */);
dispatch_width);
NIR_PASS(_, shader, brw_nir_lower_simd, dispatch_width);
@@ -7967,7 +7967,7 @@ compile_single_bs(const struct brw_compiler *compiler, void *log_data,
shader->scratch_size);
const unsigned max_dispatch_width = 16;
brw_nir_apply_key(shader, compiler, &key->base, max_dispatch_width, true);
brw_nir_apply_key(shader, compiler, &key->base, max_dispatch_width);
brw_postprocess_nir(shader, compiler, debug_enabled,
key->base.robust_buffer_access);

4
src/intel/compiler/brw_mesh.cpp
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@@ -322,7 +322,7 @@ brw_compile_task(const struct brw_compiler *compiler,
const unsigned dispatch_width = 8 << simd;
nir_shader *shader = nir_shader_clone(mem_ctx, nir);
brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */);
brw_nir_apply_key(shader, compiler, &key->base, dispatch_width);
NIR_PASS(_, shader, brw_nir_lower_load_uniforms);
NIR_PASS(_, shader, brw_nir_lower_simd, dispatch_width);
@@ -1027,7 +1027,7 @@ brw_compile_mesh(const struct brw_compiler *compiler,
if (prog_data->map.per_primitive_header_size_dw > 0)
NIR_PASS_V(shader, brw_nir_initialize_mue, &prog_data->map, dispatch_width);
brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */);
brw_nir_apply_key(shader, compiler, &key->base, dispatch_width);
NIR_PASS(_, shader, brw_nir_adjust_offset_for_arrayed_indices, &prog_data->map);
/* Load uniforms can do a better job for constants, so fold before it. */

3
src/intel/compiler/brw_nir.c
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@@ -1824,8 +1824,7 @@ void
brw_nir_apply_key(nir_shader *nir,
const struct brw_compiler *compiler,
const struct brw_base_prog_key *key,
unsigned max_subgroup_size,
bool is_scalar)
unsigned max_subgroup_size)
{
bool progress = false;

3
src/intel/compiler/brw_nir.h
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@@ -165,8 +165,7 @@ void brw_nir_apply_tcs_quads_workaround(nir_shader *nir);
void brw_nir_apply_key(nir_shader *nir,
const struct brw_compiler *compiler,
const struct brw_base_prog_key *key,
unsigned max_subgroup_size,
bool is_scalar);
unsigned max_subgroup_size);
unsigned brw_nir_api_subgroup_size(const nir_shader *nir,
unsigned hw_subgroup_size);

2
src/intel/compiler/brw_shader.cpp
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@@ -1307,7 +1307,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
nir->info.inputs_read = key->inputs_read;
nir->info.patch_inputs_read = key->patch_inputs_read;
brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
brw_nir_apply_key(nir, compiler, &key->base, 8);
brw_nir_lower_tes_inputs(nir, input_vue_map);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, debug_enabled,

2
src/intel/compiler/brw_vec4.cpp
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@@ -2552,7 +2552,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
prog_data->base.base.total_scratch = 0;
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
brw_nir_apply_key(nir, compiler, &key->base, 8);
const unsigned *assembly = NULL;

2
src/intel/compiler/brw_vec4_gs_visitor.cpp
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@@ -613,7 +613,7 @@ brw_compile_gs(const struct brw_compiler *compiler,
&c.input_vue_map, inputs_read,
nir->info.separate_shader, 1);
brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
brw_nir_apply_key(nir, compiler, &key->base, 8);
brw_nir_lower_vue_inputs(nir, &c.input_vue_map);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, debug_enabled,

2
src/intel/compiler/brw_vec4_tcs.cpp
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@@ -379,7 +379,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
nir->info.outputs_written,
nir->info.patch_outputs_written);
brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
brw_nir_apply_key(nir, compiler, &key->base, 8);
brw_nir_lower_vue_inputs(nir, &input_vue_map);
brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
key->_tes_primitive_mode);