diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index e8b795a976d..89d5b0e7e0a 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -7463,7 +7463,7 @@ brw_compile_fs(const struct brw_compiler *compiler, const struct intel_device_info *devinfo = compiler->devinfo; const unsigned max_subgroup_size = compiler->devinfo->ver >= 6 ? 32 : 16; - brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size, true); + brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size); brw_nir_lower_fs_inputs(nir, devinfo, key); brw_nir_lower_fs_outputs(nir); @@ -7841,7 +7841,7 @@ brw_compile_cs(const struct brw_compiler *compiler, nir_shader *shader = nir_shader_clone(mem_ctx, nir); brw_nir_apply_key(shader, compiler, &key->base, - dispatch_width, true /* is_scalar */); + dispatch_width); NIR_PASS(_, shader, brw_nir_lower_simd, dispatch_width); @@ -7967,7 +7967,7 @@ compile_single_bs(const struct brw_compiler *compiler, void *log_data, shader->scratch_size); const unsigned max_dispatch_width = 16; - brw_nir_apply_key(shader, compiler, &key->base, max_dispatch_width, true); + brw_nir_apply_key(shader, compiler, &key->base, max_dispatch_width); brw_postprocess_nir(shader, compiler, debug_enabled, key->base.robust_buffer_access); diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp index c6fb7a95beb..4416d6c56e2 100644 --- a/src/intel/compiler/brw_mesh.cpp +++ b/src/intel/compiler/brw_mesh.cpp @@ -322,7 +322,7 @@ brw_compile_task(const struct brw_compiler *compiler, const unsigned dispatch_width = 8 << simd; nir_shader *shader = nir_shader_clone(mem_ctx, nir); - brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */); + brw_nir_apply_key(shader, compiler, &key->base, dispatch_width); NIR_PASS(_, shader, brw_nir_lower_load_uniforms); NIR_PASS(_, shader, brw_nir_lower_simd, dispatch_width); @@ -1027,7 +1027,7 @@ brw_compile_mesh(const struct brw_compiler *compiler, if (prog_data->map.per_primitive_header_size_dw > 0) NIR_PASS_V(shader, brw_nir_initialize_mue, &prog_data->map, dispatch_width); - brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */); + brw_nir_apply_key(shader, compiler, &key->base, dispatch_width); NIR_PASS(_, shader, brw_nir_adjust_offset_for_arrayed_indices, &prog_data->map); /* Load uniforms can do a better job for constants, so fold before it. */ diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index c87d4b6ebbc..aabeb30584c 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1824,8 +1824,7 @@ void brw_nir_apply_key(nir_shader *nir, const struct brw_compiler *compiler, const struct brw_base_prog_key *key, - unsigned max_subgroup_size, - bool is_scalar) + unsigned max_subgroup_size) { bool progress = false; diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index 5ba1c99f383..6700453123e 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -165,8 +165,7 @@ void brw_nir_apply_tcs_quads_workaround(nir_shader *nir); void brw_nir_apply_key(nir_shader *nir, const struct brw_compiler *compiler, const struct brw_base_prog_key *key, - unsigned max_subgroup_size, - bool is_scalar); + unsigned max_subgroup_size); unsigned brw_nir_api_subgroup_size(const nir_shader *nir, unsigned hw_subgroup_size); diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 1dae72ed705..32bf07b3dde 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1307,7 +1307,7 @@ brw_compile_tes(const struct brw_compiler *compiler, nir->info.inputs_read = key->inputs_read; nir->info.patch_inputs_read = key->patch_inputs_read; - brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar); + brw_nir_apply_key(nir, compiler, &key->base, 8); brw_nir_lower_tes_inputs(nir, input_vue_map); brw_nir_lower_vue_outputs(nir); brw_postprocess_nir(nir, compiler, debug_enabled, diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index d5fc1909301..7725007da6d 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2552,7 +2552,7 @@ brw_compile_vs(const struct brw_compiler *compiler, prog_data->base.base.total_scratch = 0; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX]; - brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar); + brw_nir_apply_key(nir, compiler, &key->base, 8); const unsigned *assembly = NULL; diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp index 04d470f6f25..abaa784d6b9 100644 --- a/src/intel/compiler/brw_vec4_gs_visitor.cpp +++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp @@ -613,7 +613,7 @@ brw_compile_gs(const struct brw_compiler *compiler, &c.input_vue_map, inputs_read, nir->info.separate_shader, 1); - brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar); + brw_nir_apply_key(nir, compiler, &key->base, 8); brw_nir_lower_vue_inputs(nir, &c.input_vue_map); brw_nir_lower_vue_outputs(nir); brw_postprocess_nir(nir, compiler, debug_enabled, diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 08b45345139..8d60eee9bd4 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -379,7 +379,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, nir->info.outputs_written, nir->info.patch_outputs_written); - brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar); + brw_nir_apply_key(nir, compiler, &key->base, 8); brw_nir_lower_vue_inputs(nir, &input_vue_map); brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map, key->_tes_primitive_mode);