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intel/fs: Set up FB write message headers in the visitor

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Doing instruction header setup in the generator is awful for a number
of reasons.  For one, we can't schedule the header setup at all.  For
another, it means lots of implied writes which the instruction scheduler
and other passes can't properly read about.  The second isn't a huge
problem for FB writes since they always happen at the end.  We made a
similar change to sampler handling in ff4726077d.

Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand
2018-05-17 08:46:03 -07:00
parent dda31a7bbc
commit a14fb0184a
2 changed files with 86 additions and 83 deletions
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66
src/intel/compiler/brw_fs_generator.cpp
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@@ -307,9 +307,6 @@ fs_generator::fire_fb_write(fs_inst *inst,
void
fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
{
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
if (devinfo->gen < 8 && !devinfo->is_haswell) {
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
}
@@ -320,69 +317,6 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
if (inst->base_mrf >= 0)
payload = brw_message_reg(inst->base_mrf);
/* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
* move, here's g1.
*/
if (inst->header_size != 0) {
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_flag_reg(p, 0, 0);
/* On HSW, the GPU will use the predicate on SENDC, unless the header is
* present.
*/
if (prog_data->uses_kill) {
struct brw_reg pixel_mask;
if (devinfo->gen >= 6)
pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
else
pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
}
if (devinfo->gen >= 6) {
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_16);
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
brw_MOV(p,
retype(payload, BRW_REGISTER_TYPE_UD),
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
brw_pop_insn_state(p);
if (inst->target > 0 && key->replicate_alpha) {
/* Set "Source0 Alpha Present to RenderTarget" bit in message
* header.
*/
brw_OR(p,
vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
brw_imm_ud(0x1 << 11));
}
if (inst->target > 0) {
/* Set the render target index for choosing BLEND_STATE. */
brw_MOV(p, retype(vec1(suboffset(payload, 2)),
BRW_REGISTER_TYPE_UD),
brw_imm_ud(inst->target));
}
/* Set computes stencil to render target */
if (prog_data->computed_stencil) {
brw_OR(p,
vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
brw_imm_ud(0x1 << 14));
}
}
brw_pop_insn_state(p);
}
if (!runtime_check_aads_emit) {
fire_fb_write(inst, payload, implied_header, inst->mlen);
} else {