include/drm-uapi: bump headers
From drm-next at the following commit : commit 3393649977f9a8847c659e282ea290d4b703295c Merge: cbc2e82932ae ced026e959be Author: Dave Airlie <airlied@redhat.com> Date: Fri Aug 28 13:51:30 2020 +1000 Merge tag 'drm-intel-next-2020-08-24-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2901>
This commit is contained in:
Lionel Landwerlin
committed by
Marge Bot
Marge Bot
parent
a6291b1b11
commit
a0c07e41e5
@@ -13,9 +13,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
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The last update was done at the following kernel commit :
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commit 1aa63ddf726ea049279989b93b69b57ce6efd75b
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Merge: 774f1eeb18b0 14d0066b8477
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commit 3393649977f9a8847c659e282ea290d4b703295c
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Merge: cbc2e82932ae ced026e959be
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Author: Dave Airlie <airlied@redhat.com>
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Date: Wed Apr 22 10:40:34 2020 +1000
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Date: Fri Aug 28 13:51:30 2020 +1000
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Merge tag 'drm-misc-next-2020-04-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
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Merge tag 'drm-intel-next-2020-08-24-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
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@@ -502,15 +502,15 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
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/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
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#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
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/* Use NC MTYPE instead of default MTYPE */
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/* Use Non Coherent MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_NC (1 << 5)
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/* Use WC MTYPE instead of default MTYPE */
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/* Use Write Combine MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_WC (2 << 5)
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/* Use CC MTYPE instead of default MTYPE */
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/* Use Cache Coherent MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_CC (3 << 5)
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/* Use UC MTYPE instead of default MTYPE */
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/* Use UnCached MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_UC (4 << 5)
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/* Use RW MTYPE instead of default MTYPE */
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/* Use Read Write MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_RW (5 << 5)
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struct drm_amdgpu_gem_va {
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@@ -602,6 +602,10 @@ union drm_amdgpu_cs {
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*/
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#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
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/* Tell KMD to flush and invalidate caches
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*/
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#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
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struct drm_amdgpu_cs_chunk_ib {
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__u32 _pad;
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/** AMDGPU_IB_FLAG_* */
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@@ -236,6 +236,12 @@ extern "C" {
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#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
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#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
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#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
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/*
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* 2 plane YCbCr
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* index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
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* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
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*/
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#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
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/*
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* 2 plane YCbCr MSB aligned
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@@ -265,6 +271,22 @@ extern "C" {
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*/
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#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
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/* 3 plane non-subsampled (444) YCbCr
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* 16 bits per component, but only 10 bits are used and 6 bits are padded
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* index 0: Y plane, [15:0] Y:x [10:6] little endian
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* index 1: Cb plane, [15:0] Cb:x [10:6] little endian
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* index 2: Cr plane, [15:0] Cr:x [10:6] little endian
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*/
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#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
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/* 3 plane non-subsampled (444) YCrCb
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* 16 bits per component, but only 10 bits are used and 6 bits are padded
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* index 0: Y plane, [15:0] Y:x [10:6] little endian
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* index 1: Cr plane, [15:0] Cr:x [10:6] little endian
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* index 2: Cb plane, [15:0] Cb:x [10:6] little endian
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*/
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#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
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/*
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* 3 plane YCbCr
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* index 0: Y plane, [7:0] Y
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@@ -309,6 +331,7 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
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#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
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#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
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#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
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/* add more to the end as needed */
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@@ -323,8 +346,33 @@ extern "C" {
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* When adding a new token please document the layout with a code comment,
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* similar to the fourcc codes above. drm_fourcc.h is considered the
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* authoritative source for all of these.
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*
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* Generic modifier names:
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*
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* DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
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* for layouts which are common across multiple vendors. To preserve
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* compatibility, in cases where a vendor-specific definition already exists and
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* a generic name for it is desired, the common name is a purely symbolic alias
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* and must use the same numerical value as the original definition.
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*
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* Note that generic names should only be used for modifiers which describe
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* generic layouts (such as pixel re-ordering), which may have
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* independently-developed support across multiple vendors.
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*
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* In future cases where a generic layout is identified before merging with a
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* vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
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* 'NONE' could be considered. This should only be for obvious, exceptional
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* cases to avoid polluting the 'GENERIC' namespace with modifiers which only
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* apply to a single vendor.
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*
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* Generic names should not be used for cases where multiple hardware vendors
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* have implementations of the same standardised compression scheme (such as
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* AFBC). In those cases, all implementations should use the same format
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* modifier(s), reflecting the vendor of the standard.
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*/
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#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
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/*
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* Invalid Modifier
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*
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@@ -354,9 +402,12 @@ extern "C" {
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* a platform-dependent stride. On top of that the memory can apply
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* platform-depending swizzling of some higher address bits into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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* Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
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* On earlier platforms the is highly platforms specific and not useful for
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* cross-driver sharing. It exists since on a given platform it does uniquely
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* identify the layout in a simple way for i915-specific userspace, which
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* facilitated conversion of userspace to modifiers. Additionally the exact
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* format on some really old platforms is not known.
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*/
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#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
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@@ -369,9 +420,12 @@ extern "C" {
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* memory can apply platform-depending swizzling of some higher address bits
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* into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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* Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
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* On earlier platforms the is highly platforms specific and not useful for
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* cross-driver sharing. It exists since on a given platform it does uniquely
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* identify the layout in a simple way for i915-specific userspace, which
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* facilitated conversion of userspace to modifiers. Additionally the exact
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* format on some really old platforms is not known.
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*/
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#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
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@@ -521,7 +575,113 @@ extern "C" {
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#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
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/*
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* 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
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* Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
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* and Tegra GPUs starting with Tegra K1.
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*
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* Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
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* based on the architecture generation. GOBs themselves are then arranged in
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* 3D blocks, with the block dimensions (in terms of GOBs) always being a power
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* of two, and hence expressible as their log2 equivalent (E.g., "2" represents
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* a block depth or height of "4").
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*
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* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
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* in full detail.
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*
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* Macro
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* Bits Param Description
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* ---- ----- -----------------------------------------------------------------
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*
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* 3:0 h log2(height) of each block, in GOBs. Placed here for
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* compatibility with the existing
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* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
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*
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* 4:4 - Must be 1, to indicate block-linear layout. Necessary for
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* compatibility with the existing
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* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
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*
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* 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
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* size). Must be zero.
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*
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* Note there is no log2(width) parameter. Some portions of the
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* hardware support a block width of two gobs, but it is impractical
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* to use due to lack of support elsewhere, and has no known
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* benefits.
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*
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* 11:9 - Reserved (To support 2D-array textures with variable array stride
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* in blocks, specified via log2(tile width in blocks)). Must be
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* zero.
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*
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* 19:12 k Page Kind. This value directly maps to a field in the page
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* tables of all GPUs >= NV50. It affects the exact layout of bits
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* in memory and can be derived from the tuple
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*
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* (format, GPU model, compression type, samples per pixel)
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*
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* Where compression type is defined below. If GPU model were
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* implied by the format modifier, format, or memory buffer, page
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* kind would not need to be included in the modifier itself, but
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* since the modifier should define the layout of the associated
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* memory buffer independent from any device or other context, it
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* must be included here.
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*
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* 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
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* starting with Fermi GPUs. Additionally, the mapping between page
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* kind and bit layout has changed at various points.
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*
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* 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
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* 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
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* 2 = Gob Height 8, Turing+ Page Kind mapping
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* 3 = Reserved for future use.
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*
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* 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
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* bit remapping step that occurs at an even lower level than the
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* page kind and block linear swizzles. This causes the layout of
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* surfaces mapped in those SOC's GPUs to be incompatible with the
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* equivalent mapping on other GPUs in the same system.
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*
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* 0 = Tegra K1 - Tegra Parker/TX2 Layout.
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* 1 = Desktop GPU and Tegra Xavier+ Layout
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*
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* 25:23 c Lossless Framebuffer Compression type.
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*
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* 0 = none
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* 1 = ROP/3D, layout 1, exact compression format implied by Page
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* Kind field
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* 2 = ROP/3D, layout 2, exact compression format implied by Page
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* Kind field
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* 3 = CDE horizontal
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* 4 = CDE vertical
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* 5 = Reserved for future use
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* 6 = Reserved for future use
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* 7 = Reserved for future use
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*
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* 55:25 - Reserved for future use. Must be zero.
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*/
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#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
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fourcc_mod_code(NVIDIA, (0x10 | \
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((h) & 0xf) | \
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(((k) & 0xff) << 12) | \
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(((g) & 0x3) << 20) | \
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(((s) & 0x1) << 22) | \
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(((c) & 0x7) << 23)))
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/* To grandfather in prior block linear format modifiers to the above layout,
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* the page kind "0", which corresponds to "pitch/linear" and hence is unusable
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* with block-linear layouts, is remapped within drivers to the value 0xfe,
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* which corresponds to the "generic" kind used for simple single-sample
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* uncompressed color formats on Fermi - Volta GPUs.
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*/
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static __inline__ __u64
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drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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{
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if (!(modifier & 0x10) || (modifier & (0xff << 12)))
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return modifier;
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else
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return modifier | (0xfe << 12);
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}
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/*
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* 16Bx2 Block Linear layout, used by Tegra K1 and later
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*
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* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
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* vertically by a power of 2 (1 to 32 GOBs) to form a block.
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@@ -542,20 +702,20 @@ extern "C" {
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* in full detail.
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*/
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
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fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
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fourcc_mod_code(NVIDIA, 0x10)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
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fourcc_mod_code(NVIDIA, 0x11)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
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fourcc_mod_code(NVIDIA, 0x12)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
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fourcc_mod_code(NVIDIA, 0x13)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
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fourcc_mod_code(NVIDIA, 0x14)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
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fourcc_mod_code(NVIDIA, 0x15)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
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/*
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* Some Broadcom modifiers take parameters, for example the number of
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@@ -780,6 +940,18 @@ extern "C" {
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*/
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#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
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/* AFBC uncompressed storage mode
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*
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* Indicates that the buffer is using AFBC uncompressed storage mode.
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* In this mode all superblock payloads in the buffer use the uncompressed
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* storage mode, which is usually only used for data which cannot be compressed.
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* The buffer layout is the same as for AFBC buffers without USM set, this only
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* affects the storage mode of the individual superblocks. Note that even a
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* buffer without USM set may use uncompressed storage mode for some or all
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* superblocks, USM just guarantees it for all.
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*/
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#define AFBC_FORMAT_MOD_USM (1ULL << 12)
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/*
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* Arm 16x16 Block U-Interleaved modifier
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*
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@@ -804,6 +976,86 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
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/*
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* Amlogic Video Framebuffer Compression modifiers
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*
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* Amlogic uses a proprietary lossless image compression protocol and format
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* for their hardware video codec accelerators, either video decoders or
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* video input encoders.
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*
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* It considerably reduces memory bandwidth while writing and reading
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* frames in memory.
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*
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* The underlying storage is considered to be 3 components, 8bit or 10-bit
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* per component YCbCr 420, single plane :
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* - DRM_FORMAT_YUV420_8BIT
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* - DRM_FORMAT_YUV420_10BIT
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*
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* The first 8 bits of the mode defines the layout, then the following 8 bits
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* defines the options changing the layout.
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*
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* Not all combinations are valid, and different SoCs may support different
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* combinations of layout and options.
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*/
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#define __fourcc_mod_amlogic_layout_mask 0xf
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#define __fourcc_mod_amlogic_options_shift 8
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#define __fourcc_mod_amlogic_options_mask 0xf
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#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
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fourcc_mod_code(AMLOGIC, \
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((__layout) & __fourcc_mod_amlogic_layout_mask) | \
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(((__options) & __fourcc_mod_amlogic_options_mask) \
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<< __fourcc_mod_amlogic_options_shift))
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/* Amlogic FBC Layouts */
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/*
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* Amlogic FBC Basic Layout
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*
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* The basic layout is composed of:
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* - a body content organized in 64x32 superblocks with 4096 bytes per
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* superblock in default mode.
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* - a 32 bytes per 128x64 header block
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*
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* This layout is transferrable between Amlogic SoCs supporting this modifier.
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*/
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#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
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/*
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* Amlogic FBC Scatter Memory layout
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*
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* Indicates the header contains IOMMU references to the compressed
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* frames content to optimize memory access and layout.
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*
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* In this mode, only the header memory address is needed, thus the
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* content memory organization is tied to the current producer
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* execution and cannot be saved/dumped neither transferrable between
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* Amlogic SoCs supporting this modifier.
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*
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* Due to the nature of the layout, these buffers are not expected to
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* be accessible by the user-space clients, but only accessible by the
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* hardware producers and consumers.
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*
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* The user-space clients should expect a failure while trying to mmap
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* the DMA-BUF handle returned by the producer.
|
||||
*/
|
||||
#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
|
||||
|
||||
/* Amlogic FBC Layout Options Bit Mask */
|
||||
|
||||
/*
|
||||
* Amlogic FBC Memory Saving mode
|
||||
*
|
||||
* Indicates the storage is packed when pixel size is multiple of word
|
||||
* boudaries, i.e. 8bit should be stored in this mode to save allocation
|
||||
* memory.
|
||||
*
|
||||
* This mode reduces body layout to 3072 bytes per 64x32 superblock with
|
||||
* the basic layout and 3200 bytes per 64x32 superblock combined with
|
||||
* the scatter layout.
|
||||
*/
|
||||
#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -332,14 +332,19 @@ struct drm_mode_get_encoder {
|
||||
/* This is for connectors with multiple signal types. */
|
||||
/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
|
||||
enum drm_mode_subconnector {
|
||||
DRM_MODE_SUBCONNECTOR_Automatic = 0,
|
||||
DRM_MODE_SUBCONNECTOR_Unknown = 0,
|
||||
DRM_MODE_SUBCONNECTOR_DVID = 3,
|
||||
DRM_MODE_SUBCONNECTOR_DVIA = 4,
|
||||
DRM_MODE_SUBCONNECTOR_Composite = 5,
|
||||
DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
|
||||
DRM_MODE_SUBCONNECTOR_Component = 8,
|
||||
DRM_MODE_SUBCONNECTOR_SCART = 9,
|
||||
DRM_MODE_SUBCONNECTOR_Automatic = 0, /* DVI-I, TV */
|
||||
DRM_MODE_SUBCONNECTOR_Unknown = 0, /* DVI-I, TV, DP */
|
||||
DRM_MODE_SUBCONNECTOR_VGA = 1, /* DP */
|
||||
DRM_MODE_SUBCONNECTOR_DVID = 3, /* DVI-I DP */
|
||||
DRM_MODE_SUBCONNECTOR_DVIA = 4, /* DVI-I */
|
||||
DRM_MODE_SUBCONNECTOR_Composite = 5, /* TV */
|
||||
DRM_MODE_SUBCONNECTOR_SVIDEO = 6, /* TV */
|
||||
DRM_MODE_SUBCONNECTOR_Component = 8, /* TV */
|
||||
DRM_MODE_SUBCONNECTOR_SCART = 9, /* TV */
|
||||
DRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */
|
||||
DRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */
|
||||
DRM_MODE_SUBCONNECTOR_Native = 15, /* DP */
|
||||
DRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */
|
||||
};
|
||||
|
||||
#define DRM_MODE_CONNECTOR_Unknown 0
|
||||
@@ -497,7 +502,7 @@ struct drm_mode_fb_cmd2 {
|
||||
* In case of planar formats, this ioctl allows up to 4
|
||||
* buffer objects with offsets and pitches per plane.
|
||||
* The pitch and offset order is dictated by the fourcc,
|
||||
* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
|
||||
* e.g. NV12 (https://fourcc.org/yuv.php#NV12) is described as:
|
||||
*
|
||||
* YUV 4:2:0 image with a plane of 8 bit Y samples
|
||||
* followed by an interleaved U/V plane containing
|
||||
|
||||
@@ -55,7 +55,7 @@ extern "C" {
|
||||
* cause the related events to not be seen.
|
||||
*
|
||||
* I915_RESET_UEVENT - Event is generated just before an attempt to reset the
|
||||
* the GPU. The value supplied with the event is always 1. NOTE: Disable
|
||||
* GPU. The value supplied with the event is always 1. NOTE: Disable
|
||||
* reset via module parameter will cause this event to not be seen.
|
||||
*/
|
||||
#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
|
||||
@@ -619,6 +619,12 @@ typedef struct drm_i915_irq_wait {
|
||||
*/
|
||||
#define I915_PARAM_PERF_REVISION 54
|
||||
|
||||
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
|
||||
* timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
|
||||
* I915_EXEC_USE_EXTENSIONS.
|
||||
*/
|
||||
#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
|
||||
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
@@ -1046,6 +1052,38 @@ struct drm_i915_gem_exec_fence {
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* See drm_i915_gem_execbuffer_ext_timeline_fences.
|
||||
*/
|
||||
#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
|
||||
|
||||
/**
|
||||
* This structure describes an array of drm_syncobj and associated points for
|
||||
* timeline variants of drm_syncobj. It is invalid to append this structure to
|
||||
* the execbuf if I915_EXEC_FENCE_ARRAY is set.
|
||||
*/
|
||||
struct drm_i915_gem_execbuffer_ext_timeline_fences {
|
||||
struct i915_user_extension base;
|
||||
|
||||
/**
|
||||
* Number of element in the handles_ptr & value_ptr arrays.
|
||||
*/
|
||||
__u64 fence_count;
|
||||
|
||||
/**
|
||||
* Pointer to an array of struct drm_i915_gem_exec_fence of length
|
||||
* fence_count.
|
||||
*/
|
||||
__u64 handles_ptr;
|
||||
|
||||
/**
|
||||
* Pointer to an array of u64 values of length fence_count. Values
|
||||
* must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
|
||||
* drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
|
||||
*/
|
||||
__u64 values_ptr;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_execbuffer2 {
|
||||
/**
|
||||
* List of gem_exec_object2 structs
|
||||
@@ -1062,8 +1100,14 @@ struct drm_i915_gem_execbuffer2 {
|
||||
__u32 num_cliprects;
|
||||
/**
|
||||
* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
|
||||
* is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
|
||||
* struct drm_i915_gem_exec_fence *fences.
|
||||
* & I915_EXEC_USE_EXTENSIONS are not set.
|
||||
*
|
||||
* If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
|
||||
* of struct drm_i915_gem_exec_fence and num_cliprects is the length
|
||||
* of the array.
|
||||
*
|
||||
* If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
|
||||
* single struct i915_user_extension and num_cliprects is 0.
|
||||
*/
|
||||
__u64 cliprects_ptr;
|
||||
#define I915_EXEC_RING_MASK (0x3f)
|
||||
@@ -1181,7 +1225,16 @@ struct drm_i915_gem_execbuffer2 {
|
||||
*/
|
||||
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
|
||||
/*
|
||||
* Setting I915_EXEC_USE_EXTENSIONS implies that
|
||||
* drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
|
||||
* list of i915_user_extension. Each i915_user_extension node is the base of a
|
||||
* larger structure. The list of supported structures are listed in the
|
||||
* drm_i915_gem_execbuffer_ext enum.
|
||||
*/
|
||||
#define I915_EXEC_USE_EXTENSIONS (1 << 21)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
|
||||
|
||||
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
|
||||
#define i915_execbuffer2_set_context_id(eb2, context) \
|
||||
@@ -1934,7 +1987,7 @@ enum drm_i915_perf_property_id {
|
||||
|
||||
/**
|
||||
* The value specifies which set of OA unit metrics should be
|
||||
* be configured, defining the contents of any OA unit reports.
|
||||
* configured, defining the contents of any OA unit reports.
|
||||
*
|
||||
* This property is available in perf revision 1.
|
||||
*/
|
||||
|
||||
@@ -252,8 +252,8 @@ struct drm_msm_gem_submit {
|
||||
__u64 cmds; /* in, ptr to array of submit_cmd's */
|
||||
__s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
|
||||
__u32 queueid; /* in, submitqueue id */
|
||||
__u64 in_syncobjs; /* in, ptr to to array of drm_msm_gem_submit_syncobj */
|
||||
__u64 out_syncobjs; /* in, ptr to to array of drm_msm_gem_submit_syncobj */
|
||||
__u64 in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
|
||||
__u64 out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
|
||||
__u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
|
||||
__u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
|
||||
__u32 syncobj_stride; /* in, stride of syncobj arrays. */
|
||||
|
||||
Reference in New Issue
Block a user