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radv: copy need_indirect_descriptor_sets to radv_cmd_state

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22209>
This commit is contained in:
Samuel Pitoiset
2023-03-22 17:50:21 +01:00
committed by Marge Bot
parent eeefe18f05
commit a0baefa033
2 changed files with 11 additions and 7 deletions
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17
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -4463,7 +4463,7 @@ radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
static void static void
radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer, radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline, VkPipelineBindPoint bind_point) VkPipelineBindPoint bind_point)
{ {
struct radv_descriptor_state *descriptors_state = struct radv_descriptor_state *descriptors_state =
radv_get_descriptors_state(cmd_buffer, bind_point); radv_get_descriptors_state(cmd_buffer, bind_point);
@@ -4514,7 +4514,7 @@ radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
ALWAYS_INLINE static void ALWAYS_INLINE static void
radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stages, radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stages,
struct radv_pipeline *pipeline, VkPipelineBindPoint bind_point) VkPipelineBindPoint bind_point)
{ {
struct radv_descriptor_state *descriptors_state = struct radv_descriptor_state *descriptors_state =
radv_get_descriptors_state(cmd_buffer, bind_point); radv_get_descriptors_state(cmd_buffer, bind_point);
@@ -4525,10 +4525,10 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags st
if (!descriptors_state->dirty) if (!descriptors_state->dirty)
return; return;
flush_indirect_descriptors = pipeline->need_indirect_descriptor_sets; flush_indirect_descriptors = descriptors_state->need_indirect_descriptor_sets;
if (flush_indirect_descriptors) if (flush_indirect_descriptors)
radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline, bind_point); radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
ASSERTED unsigned cdw_max = ASSERTED unsigned cdw_max =
radeon_check_space(device->ws, cs, MAX_SETS * MESA_VULKAN_SHADER_STAGES * 4); radeon_check_space(device->ws, cs, MAX_SETS * MESA_VULKAN_SHADER_STAGES * 4);
@@ -5110,7 +5110,7 @@ radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
radv_flush_streamout_descriptors(cmd_buffer); radv_flush_streamout_descriptors(cmd_buffer);
VkShaderStageFlags stages = VK_SHADER_STAGE_ALL_GRAPHICS; VkShaderStageFlags stages = VK_SHADER_STAGE_ALL_GRAPHICS;
radv_flush_descriptors(cmd_buffer, stages, &pipeline->base, VK_PIPELINE_BIND_POINT_GRAPHICS); radv_flush_descriptors(cmd_buffer, stages, VK_PIPELINE_BIND_POINT_GRAPHICS);
const VkShaderStageFlags pc_stages = const VkShaderStageFlags pc_stages =
radv_must_flush_constants(cmd_buffer, &pipeline->base, stages); radv_must_flush_constants(cmd_buffer, &pipeline->base, stages);
@@ -6593,6 +6593,9 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
break; break;
} }
cmd_buffer->descriptors[vk_to_bind_point(pipelineBindPoint)].need_indirect_descriptor_sets =
pipeline->need_indirect_descriptor_sets;
if (cmd_buffer->device->shader_use_invisible_vram) if (cmd_buffer->device->shader_use_invisible_vram)
cmd_buffer->shader_upload_seq = cmd_buffer->shader_upload_seq =
MAX2(cmd_buffer->shader_upload_seq, pipeline->shader_upload_seq); MAX2(cmd_buffer->shader_upload_seq, pipeline->shader_upload_seq);
@@ -8998,7 +9001,7 @@ radv_before_taskmesh_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_
} }
} }
radv_flush_descriptors(cmd_buffer, stages, &pipeline->base, VK_PIPELINE_BIND_POINT_GRAPHICS); radv_flush_descriptors(cmd_buffer, stages, VK_PIPELINE_BIND_POINT_GRAPHICS);
const VkShaderStageFlags pc_stages = const VkShaderStageFlags pc_stages =
radv_must_flush_constants(cmd_buffer, &pipeline->base, stages); radv_must_flush_constants(cmd_buffer, &pipeline->base, stages);
@@ -9569,7 +9572,7 @@ radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer,
struct radv_compute_pipeline *pipeline, struct radv_compute_pipeline *pipeline,
VkPipelineBindPoint bind_point) VkPipelineBindPoint bind_point)
{ {
radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT, &pipeline->base, bind_point); radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT, bind_point);
const VkShaderStageFlags stages = bind_point == VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR const VkShaderStageFlags stages = bind_point == VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR
? RADV_RT_STAGE_BITS ? RADV_RT_STAGE_BITS
: VK_SHADER_STAGE_COMPUTE_BIT; : VK_SHADER_STAGE_COMPUTE_BIT;

1
src/amd/vulkan/radv_private.h
View File

@@ -1550,6 +1550,7 @@ struct radv_descriptor_state {
struct radv_push_descriptor_set push_set; struct radv_push_descriptor_set push_set;
uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS]; uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
uint64_t descriptor_buffers[MAX_SETS]; uint64_t descriptor_buffers[MAX_SETS];
bool need_indirect_descriptor_sets;
}; };
enum rgp_flush_bits { enum rgp_flush_bits {