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intel/fs: Don't read reg.base_offset

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It's not set in the new intrinsics path.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>
This commit is contained in:
Alyssa Rosenzweig
2023-07-20 08:22:58 -04:00
committed by Marge Bot
parent 01965a2fe9
commit a08286f993
1 changed files with 2 additions and 8 deletions
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10
src/intel/compiler/brw_fs_nir.cpp
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@@ -2015,13 +2015,10 @@ fs_visitor::get_nir_src(const nir_src &src)
} }
} else { } else {
nir_intrinsic_instr *decl_reg = nir_reg_get_decl(load_reg->src[0].ssa); nir_intrinsic_instr *decl_reg = nir_reg_get_decl(load_reg->src[0].ssa);
const unsigned num_components =
nir_intrinsic_num_components(decl_reg);
/* We don't handle indirects on locals */ /* We don't handle indirects on locals */
assert(nir_intrinsic_base(load_reg) == 0); assert(nir_intrinsic_base(load_reg) == 0);
assert(load_reg->intrinsic != nir_intrinsic_load_reg_indirect); assert(load_reg->intrinsic != nir_intrinsic_load_reg_indirect);
reg = offset(nir_ssa_values[decl_reg->dest.ssa.index], bld, reg = nir_ssa_values[decl_reg->dest.ssa.index];
src.reg.base_offset * num_components);
} }
if (nir_src_bit_size(src) == 64 && devinfo->ver == 7) { if (nir_src_bit_size(src) == 64 && devinfo->ver == 7) {
@@ -2074,13 +2071,10 @@ fs_visitor::get_nir_dest(const nir_dest &dest)
} else { } else {
nir_intrinsic_instr *decl_reg = nir_intrinsic_instr *decl_reg =
nir_reg_get_decl(store_reg->src[1].ssa); nir_reg_get_decl(store_reg->src[1].ssa);
const unsigned num_components =
nir_intrinsic_num_components(decl_reg);
/* We don't handle indirects on locals */ /* We don't handle indirects on locals */
assert(nir_intrinsic_base(store_reg) == 0); assert(nir_intrinsic_base(store_reg) == 0);
assert(store_reg->intrinsic != nir_intrinsic_store_reg_indirect); assert(store_reg->intrinsic != nir_intrinsic_store_reg_indirect);
return offset(nir_ssa_values[decl_reg->dest.ssa.index], bld, return nir_ssa_values[decl_reg->dest.ssa.index];
dest.reg.base_offset * num_components);
} }
} }