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docs: Adreno aXXX -> Adreno XXX

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The names of these are "Adreno XXX" or "aXXX", not "Adreno aXXX".

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19297>
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Erik Faye-Lund
2022-10-25 11:42:42 +02:00
committed by Marge Bot
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docs/drivers/freedreno/ir3-notes.rst
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IR3 NOTES
=========
Some notes about ir3, the compiler and machine-specific IR for the shader ISA introduced with Adreno a3xx. The same shader ISA is present, with some small differences, in Adreno a4xx.
Some notes about ir3, the compiler and machine-specific IR for the shader ISA introduced with Adreno 3xx. The same shader ISA is present, with some small differences, in Adreno 4xx.
Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or NOPs). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like: