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compiler: Use util/bitset.h for system_values_read

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It is currently a bitset on top of a uint64_t but there are already
more than 64 values.  Change to use BITSET to cover all the
SYSTEM_VALUE_MAX bits.

Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8585>
This commit is contained in:
Caio Marcelo de Oliveira Filho
2021-01-19 17:14:28 -08:00
committed by Marge Bot
parent ecd0ae09f9
commit 9f3d5e99ea
27 changed files with 175 additions and 199 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
src/broadcom/compiler/nir_to_vir.c
View File

@@ -1620,14 +1620,16 @@ ntq_setup_vs_inputs(struct v3d_compile *c)
unsigned num_components = 0; unsigned num_components = 0;
uint32_t vpm_components_queued = 0; uint32_t vpm_components_queued = 0;
bool uses_iid = c->s->info.system_values_read & bool uses_iid = BITSET_TEST(c->s->info.system_values_read,
(1ull << SYSTEM_VALUE_INSTANCE_ID | SYSTEM_VALUE_INSTANCE_ID) ||
1ull << SYSTEM_VALUE_INSTANCE_INDEX); BITSET_TEST(c->s->info.system_values_read,
bool uses_biid = c->s->info.system_values_read & SYSTEM_VALUE_INSTANCE_INDEX);
(1ull << SYSTEM_VALUE_BASE_INSTANCE); bool uses_biid = BITSET_TEST(c->s->info.system_values_read,
bool uses_vid = c->s->info.system_values_read & SYSTEM_VALUE_BASE_INSTANCE);
(1ull << SYSTEM_VALUE_VERTEX_ID | bool uses_vid = BITSET_TEST(c->s->info.system_values_read,
1ull << SYSTEM_VALUE_VERTEX_ID_ZERO_BASE); SYSTEM_VALUE_VERTEX_ID) ||
BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
num_components += uses_iid; num_components += uses_iid;
num_components += uses_biid; num_components += uses_biid;
@@ -2079,16 +2081,16 @@ ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
* be slower if the VPM unit is busy with another QPU. * be slower if the VPM unit is busy with another QPU.
*/ */
int index = 0; int index = 0;
if (c->s->info.system_values_read & if (BITSET_TEST(c->s->info.system_values_read,
(1ull << SYSTEM_VALUE_INSTANCE_ID)) { SYSTEM_VALUE_INSTANCE_ID)) {
index++; index++;
} }
if (c->s->info.system_values_read & if (BITSET_TEST(c->s->info.system_values_read,
(1ull << SYSTEM_VALUE_BASE_INSTANCE)) { SYSTEM_VALUE_BASE_INSTANCE)) {
index++; index++;
} }
if (c->s->info.system_values_read & if (BITSET_TEST(c->s->info.system_values_read,
(1ull << SYSTEM_VALUE_VERTEX_ID)) { SYSTEM_VALUE_VERTEX_ID)) {
index++; index++;
} }
for (int i = 0; i < offset; i++) for (int i = 0; i < offset; i++)
@@ -3130,16 +3132,18 @@ nir_to_vir(struct v3d_compile *c)
c->uses_implicit_point_line_varyings = true; c->uses_implicit_point_line_varyings = true;
} else if (c->fs_key->is_lines && } else if (c->fs_key->is_lines &&
(c->devinfo->ver < 40 || (c->devinfo->ver < 40 ||
(c->s->info.system_values_read & BITSET_TEST(c->s->info.system_values_read,
BITFIELD64_BIT(SYSTEM_VALUE_LINE_COORD)))) { SYSTEM_VALUE_LINE_COORD))) {
c->line_x = emit_fragment_varying(c, NULL, -1, 0, 0); c->line_x = emit_fragment_varying(c, NULL, -1, 0, 0);
c->uses_implicit_point_line_varyings = true; c->uses_implicit_point_line_varyings = true;
} }
c->force_per_sample_msaa = c->force_per_sample_msaa =
c->s->info.fs.uses_sample_qualifier || c->s->info.fs.uses_sample_qualifier ||
(c->s->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID | BITSET_TEST(c->s->info.system_values_read,
SYSTEM_BIT_SAMPLE_POS)); SYSTEM_VALUE_SAMPLE_ID) ||
BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_SAMPLE_POS);
break; break;
case MESA_SHADER_COMPUTE: case MESA_SHADER_COMPUTE:
/* Set up the TSO for barriers, assuming we do some. */ /* Set up the TSO for barriers, assuming we do some. */

22
src/broadcom/compiler/vir.c
View File

@@ -640,16 +640,18 @@ v3d_vs_set_prog_data(struct v3d_compile *c,
prog_data->vpm_input_size += c->vattr_sizes[i]; prog_data->vpm_input_size += c->vattr_sizes[i];
} }
prog_data->uses_vid = (c->s->info.system_values_read & prog_data->uses_vid = BITSET_TEST(c->s->info.system_values_read,
(1ull << SYSTEM_VALUE_VERTEX_ID | SYSTEM_VALUE_VERTEX_ID) ||
1ull << SYSTEM_VALUE_VERTEX_ID_ZERO_BASE)); BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
prog_data->uses_biid = (c->s->info.system_values_read & prog_data->uses_biid = BITSET_TEST(c->s->info.system_values_read,
(1ull << SYSTEM_VALUE_BASE_INSTANCE)); SYSTEM_VALUE_BASE_INSTANCE);
prog_data->uses_iid = (c->s->info.system_values_read & prog_data->uses_iid = BITSET_TEST(c->s->info.system_values_read,
(1ull << SYSTEM_VALUE_INSTANCE_ID | SYSTEM_VALUE_INSTANCE_ID) ||
1ull << SYSTEM_VALUE_INSTANCE_INDEX)); BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_INSTANCE_INDEX);
if (prog_data->uses_vid) if (prog_data->uses_vid)
prog_data->vpm_input_size++; prog_data->vpm_input_size++;
@@ -703,8 +705,8 @@ v3d_gs_set_prog_data(struct v3d_compile *c,
* it after reading it if necessary, so it doesn't add to the VPM * it after reading it if necessary, so it doesn't add to the VPM
* size requirements. * size requirements.
*/ */
prog_data->uses_pid = (c->s->info.system_values_read & prog_data->uses_pid = BITSET_TEST(c->s->info.system_values_read,
(1ull << SYSTEM_VALUE_PRIMITIVE_ID)); SYSTEM_VALUE_PRIMITIVE_ID);
/* Output segment size is in sectors (8 rows of 32 bits per channel) */ /* Output segment size is in sectors (8 rows of 32 bits per channel) */
prog_data->vpm_output_size = align(c->vpm_output_size, 8) / 8; prog_data->vpm_output_size = align(c->vpm_output_size, 8) / 8;

4
src/compiler/glsl/ir_set_program_inouts.cpp
View File

@@ -124,7 +124,7 @@ mark(struct gl_program *prog, ir_variable *var, int offset, int len,
prog->info.fs.uses_sample_qualifier |= var->data.sample; prog->info.fs.uses_sample_qualifier |= var->data.sample;
} }
} else if (var->data.mode == ir_var_system_value) { } else if (var->data.mode == ir_var_system_value) {
prog->info.system_values_read |= bitfield; BITSET_SET(prog->info.system_values_read, idx);
} else { } else {
assert(var->data.mode == ir_var_shader_out); assert(var->data.mode == ir_var_shader_out);
if (is_patch_generic) { if (is_patch_generic) {
@@ -432,7 +432,7 @@ do_set_program_inouts(exec_list *instructions, struct gl_program *prog,
prog->info.outputs_read = 0; prog->info.outputs_read = 0;
prog->info.patch_inputs_read = 0; prog->info.patch_inputs_read = 0;
prog->info.patch_outputs_written = 0; prog->info.patch_outputs_written = 0;
prog->info.system_values_read = 0; BITSET_ZERO(prog->info.system_values_read);
if (shader_stage == MESA_SHADER_FRAGMENT) { if (shader_stage == MESA_SHADER_FRAGMENT) {
prog->info.fs.uses_sample_qualifier = false; prog->info.fs.uses_sample_qualifier = false;
prog->info.fs.uses_discard = false; prog->info.fs.uses_discard = false;

34
src/compiler/nir/nir_gather_info.c
View File

@@ -495,40 +495,40 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
case nir_intrinsic_load_barycentric_model: case nir_intrinsic_load_barycentric_model:
case nir_intrinsic_load_gs_header_ir3: case nir_intrinsic_load_gs_header_ir3:
case nir_intrinsic_load_tcs_header_ir3: case nir_intrinsic_load_tcs_header_ir3:
shader->info.system_values_read |= BITSET_SET(shader->info.system_values_read,
(1ull << nir_system_value_from_intrinsic(instr->intrinsic)); nir_system_value_from_intrinsic(instr->intrinsic));
break; break;
case nir_intrinsic_load_barycentric_pixel: case nir_intrinsic_load_barycentric_pixel:
if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH || if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) { nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
shader->info.system_values_read |= BITSET_SET(shader->info.system_values_read,
BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL); SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
} else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) { } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
shader->info.system_values_read |= BITSET_SET(shader->info.system_values_read,
BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL); SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
} }
break; break;
case nir_intrinsic_load_barycentric_centroid: case nir_intrinsic_load_barycentric_centroid:
if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH || if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) { nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
shader->info.system_values_read |= BITSET_SET(shader->info.system_values_read,
BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID); SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
} else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) { } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
shader->info.system_values_read |= BITSET_SET(shader->info.system_values_read,
BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID); SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
} }
break; break;
case nir_intrinsic_load_barycentric_sample: case nir_intrinsic_load_barycentric_sample:
if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH || if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) { nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
shader->info.system_values_read |= BITSET_SET(shader->info.system_values_read,
BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE); SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
} else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) { } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
shader->info.system_values_read |= BITSET_SET(shader->info.system_values_read,
BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE); SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
} }
if (shader->info.stage == MESA_SHADER_FRAGMENT) if (shader->info.stage == MESA_SHADER_FRAGMENT)
shader->info.fs.uses_sample_qualifier = true; shader->info.fs.uses_sample_qualifier = true;
@@ -831,7 +831,7 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
shader->info.patch_outputs_read = 0; shader->info.patch_outputs_read = 0;
shader->info.patch_inputs_read = 0; shader->info.patch_inputs_read = 0;
shader->info.patch_outputs_written = 0; shader->info.patch_outputs_written = 0;
shader->info.system_values_read = 0; BITSET_ZERO(shader->info.system_values_read);
shader->info.inputs_read_indirectly = 0; shader->info.inputs_read_indirectly = 0;
shader->info.outputs_accessed_indirectly = 0; shader->info.outputs_accessed_indirectly = 0;
shader->info.patch_inputs_read_indirectly = 0; shader->info.patch_inputs_read_indirectly = 0;
@@ -864,8 +864,8 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
if (shader->info.stage == MESA_SHADER_FRAGMENT && if (shader->info.stage == MESA_SHADER_FRAGMENT &&
(shader->info.fs.uses_sample_qualifier || (shader->info.fs.uses_sample_qualifier ||
(shader->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_ID)) || (BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
shader->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_POS))) { BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS)))) {
/* This shouldn't be cleared because if optimizations remove all /* This shouldn't be cleared because if optimizations remove all
* sample-qualified inputs and that pass is run again, the sample * sample-qualified inputs and that pass is run again, the sample
* shading must stay enabled. * shading must stay enabled.

9
src/compiler/shader_enums.h
View File

@@ -382,15 +382,6 @@ const char *gl_varying_slot_name_for_stage(gl_varying_slot slot,
#define VARYING_BIT_VAR(V) BITFIELD64_BIT(VARYING_SLOT_VAR0 + (V)) #define VARYING_BIT_VAR(V) BITFIELD64_BIT(VARYING_SLOT_VAR0 + (V))
/*@}*/ /*@}*/
/**
* Bitflags for system values.
*/
#define SYSTEM_BIT_SAMPLE_ID ((uint64_t)1 << SYSTEM_VALUE_SAMPLE_ID)
#define SYSTEM_BIT_SAMPLE_POS ((uint64_t)1 << SYSTEM_VALUE_SAMPLE_POS)
#define SYSTEM_BIT_SAMPLE_MASK_IN ((uint64_t)1 << SYSTEM_VALUE_SAMPLE_MASK_IN)
#define SYSTEM_BIT_LOCAL_INVOCATION_ID ((uint64_t)1 << SYSTEM_VALUE_LOCAL_INVOCATION_ID)
#define SYSTEM_BIT_FRONT_FACE ((uint64_t)1 << SYSTEM_VALUE_FRONT_FACE)
/** /**
* If the gl_register_file is PROGRAM_SYSTEM_VALUE, the register index will be * If the gl_register_file is PROGRAM_SYSTEM_VALUE, the register index will be
* one of these values. If a NIR variable's mode is nir_var_system_value, it * one of these values. If a NIR variable's mode is nir_var_system_value, it

3
src/compiler/shader_info.h
View File

@@ -25,6 +25,7 @@
#ifndef SHADER_INFO_H #ifndef SHADER_INFO_H
#define SHADER_INFO_H #define SHADER_INFO_H
#include "util/bitset.h"
#include "shader_enums.h" #include "shader_enums.h"
#include <stdint.h> #include <stdint.h>
@@ -144,7 +145,7 @@ typedef struct shader_info {
/* Which outputs are actually read */ /* Which outputs are actually read */
uint64_t outputs_read; uint64_t outputs_read;
/* Which system values are actually read */ /* Which system values are actually read */
uint64_t system_values_read; BITSET_DECLARE(system_values_read, SYSTEM_VALUE_MAX);
/* Which patch inputs are actually read */ /* Which patch inputs are actually read */
uint32_t patch_inputs_read; uint32_t patch_inputs_read;

2
src/gallium/auxiliary/nir/nir_to_tgsi.c
View File

@@ -2789,7 +2789,7 @@ nir_to_tgsi(struct nir_shader *s,
* gl-2.1-polygon-stipple-fs on softpipe. * gl-2.1-polygon-stipple-fs on softpipe.
*/ */
if ((s->info.inputs_read & VARYING_BIT_POS) || if ((s->info.inputs_read & VARYING_BIT_POS) ||
(s->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD))) { BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRAG_COORD)) {
ureg_property(c->ureg, TGSI_PROPERTY_FS_COORD_ORIGIN, ureg_property(c->ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
s->info.fs.origin_upper_left ? s->info.fs.origin_upper_left ?
TGSI_FS_COORD_ORIGIN_UPPER_LEFT : TGSI_FS_COORD_ORIGIN_UPPER_LEFT :

4
src/gallium/auxiliary/nir/tgsi_to_nir.c
View File

@@ -653,8 +653,8 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
load = nir_swizzle(b, load, SWIZ(X, Y, Z, Z), 4); load = nir_swizzle(b, load, SWIZ(X, Y, Z, Z), 4);
src = nir_src_for_ssa(load); src = nir_src_for_ssa(load);
b->shader->info.system_values_read |= BITSET_SET(b->shader->info.system_values_read,
(1ull << nir_system_value_from_intrinsic(op)); nir_system_value_from_intrinsic(op));
break; break;
} }

2
src/gallium/drivers/d3d12/d3d12_compiler.cpp
View File

@@ -521,7 +521,7 @@ validate_geometry_shader_variant(struct d3d12_selection_context *sel_ctx)
if (sel_ctx->fill_mode_lowered != PIPE_POLYGON_MODE_FILL) { if (sel_ctx->fill_mode_lowered != PIPE_POLYGON_MODE_FILL) {
key.fill_mode = sel_ctx->fill_mode_lowered; key.fill_mode = sel_ctx->fill_mode_lowered;
key.cull_mode = sel_ctx->cull_mode_lowered; key.cull_mode = sel_ctx->cull_mode_lowered;
key.has_front_face = (fs->initial->info.system_values_read & SYSTEM_BIT_FRONT_FACE) ? 1 : 0; key.has_front_face = BITSET_TEST(fs->initial->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
if (key.cull_mode != PIPE_FACE_NONE || key.has_front_face) if (key.cull_mode != PIPE_FACE_NONE || key.has_front_face)
key.front_ccw = ctx->gfx_pipeline_state.rast->base.front_ccw ^ (ctx->flip_y < 0); key.front_ccw = ctx->gfx_pipeline_state.rast->base.front_ccw ^ (ctx->flip_y < 0);
key.edge_flag_fix = needs_edge_flag_fix(ctx->initial_api_prim); key.edge_flag_fix = needs_edge_flag_fix(ctx->initial_api_prim);

2
src/gallium/drivers/iris/iris_draw.c
View File

@@ -92,7 +92,7 @@ iris_update_draw_info(struct iris_context *ice,
const struct shader_info *tcs_info = const struct shader_info *tcs_info =
iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL); iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL);
if (tcs_info && if (tcs_info &&
tcs_info->system_values_read & (1ull << SYSTEM_VALUE_VERTICES_IN)) { BITSET_TEST(tcs_info->system_values_read, SYSTEM_VALUE_VERTICES_IN)) {
ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TCS; ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TCS;
ice->state.shaders[MESA_SHADER_TESS_CTRL].sysvals_need_upload = true; ice->state.shaders[MESA_SHADER_TESS_CTRL].sysvals_need_upload = true;
} }

2
src/gallium/drivers/iris/iris_program.c
View File

@@ -1529,7 +1529,7 @@ iris_update_compiled_tes(struct iris_context *ice)
/* TODO: Could compare and avoid flagging this. */ /* TODO: Could compare and avoid flagging this. */
const struct shader_info *tes_info = &ish->nir->info; const struct shader_info *tes_info = &ish->nir->info;
if (tes_info->system_values_read & (1ull << SYSTEM_VALUE_VERTICES_IN)) { if (BITSET_TEST(tes_info->system_values_read, SYSTEM_VALUE_VERTICES_IN)) {
ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TES; ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TES;
ice->state.shaders[MESA_SHADER_TESS_EVAL].sysvals_need_upload = true; ice->state.shaders[MESA_SHADER_TESS_EVAL].sysvals_need_upload = true;
} }

20
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
View File

@@ -983,10 +983,8 @@ bool Converter::assignSlots() {
info_out->numOutputs = 0; info_out->numOutputs = 0;
info_out->numSysVals = 0; info_out->numSysVals = 0;
for (uint8_t i = 0; i < SYSTEM_VALUE_MAX; ++i) { uint8_t i;
if (!(nir->info.system_values_read & 1ull << i)) BITSET_FOREACH_SET(i, nir->info.system_values_read, SYSTEM_VALUE_MAX) {
continue;
info_out->sv[info_out->numSysVals].sn = tgsi_get_sysval_semantic(i); info_out->sv[info_out->numSysVals].sn = tgsi_get_sysval_semantic(i);
info_out->sv[info_out->numSysVals].si = 0; info_out->sv[info_out->numSysVals].si = 0;
info_out->sv[info_out->numSysVals].input = 0; // TODO inferSysValDirection(sn); info_out->sv[info_out->numSysVals].input = 0; // TODO inferSysValDirection(sn);
@@ -1299,14 +1297,14 @@ Converter::parseNIR()
case Program::TYPE_FRAGMENT: case Program::TYPE_FRAGMENT:
info_out->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests; info_out->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests;
prog->persampleInvocation = prog->persampleInvocation =
(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_ID) || BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS); BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS);
info_out->prop.fp.postDepthCoverage = nir->info.fs.post_depth_coverage; info_out->prop.fp.postDepthCoverage = nir->info.fs.post_depth_coverage;
info_out->prop.fp.readsSampleLocations = info_out->prop.fp.readsSampleLocations =
(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS); BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS);
info_out->prop.fp.usesDiscard = nir->info.fs.uses_discard || nir->info.fs.uses_demote; info_out->prop.fp.usesDiscard = nir->info.fs.uses_discard || nir->info.fs.uses_demote;
info_out->prop.fp.usesSampleMaskIn = info_out->prop.fp.usesSampleMaskIn =
!!(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN); !BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
break; break;
case Program::TYPE_GEOMETRY: case Program::TYPE_GEOMETRY:
info_out->prop.gp.instanceCount = nir->info.gs.invocations; info_out->prop.gp.instanceCount = nir->info.gs.invocations;
@@ -1327,9 +1325,9 @@ Converter::parseNIR()
break; break;
case Program::TYPE_VERTEX: case Program::TYPE_VERTEX:
info_out->prop.vp.usesDrawParameters = info_out->prop.vp.usesDrawParameters =
(nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) || BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX) ||
(nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) || BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE) ||
(nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)); BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
break; break;
default: default:
break; break;

8
src/gallium/drivers/panfrost/pan_assemble.c
View File

@@ -302,8 +302,8 @@ panfrost_shader_compile(struct panfrost_context *ctx,
state->sysval_count = program->sysval_count; state->sysval_count = program->sysval_count;
memcpy(state->sysval, program->sysvals, sizeof(state->sysval[0]) * state->sysval_count); memcpy(state->sysval, program->sysvals, sizeof(state->sysval[0]) * state->sysval_count);
bool vertex_id = s->info.system_values_read & (1 << SYSTEM_VALUE_VERTEX_ID); bool vertex_id = BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_VERTEX_ID);
bool instance_id = s->info.system_values_read & (1 << SYSTEM_VALUE_INSTANCE_ID); bool instance_id = BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
state->writes_global = s->info.writes_memory; state->writes_global = s->info.writes_memory;
@@ -361,10 +361,10 @@ panfrost_shader_compile(struct panfrost_context *ctx,
state->stack_size = program->tls_size; state->stack_size = program->tls_size;
state->reads_frag_coord = (s->info.inputs_read & (1 << VARYING_SLOT_POS)) || state->reads_frag_coord = (s->info.inputs_read & (1 << VARYING_SLOT_POS)) ||
(s->info.system_values_read & (1 << SYSTEM_VALUE_FRAG_COORD)); BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRAG_COORD);
state->reads_point_coord = s->info.inputs_read & (1 << VARYING_SLOT_PNTC); state->reads_point_coord = s->info.inputs_read & (1 << VARYING_SLOT_PNTC);
state->reads_face = (s->info.inputs_read & (1 << VARYING_SLOT_FACE)) || state->reads_face = (s->info.inputs_read & (1 << VARYING_SLOT_FACE)) ||
(s->info.system_values_read & (1 << SYSTEM_VALUE_FRONT_FACE)); BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
state->writes_point_size = s->info.outputs_written & (1 << VARYING_SLOT_PSIZ); state->writes_point_size = s->info.outputs_written & (1 << VARYING_SLOT_PSIZ);
if (outputs_written) if (outputs_written)

55
src/gallium/drivers/radeonsi/si_shader_nir.c
View File

@@ -374,28 +374,28 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir); info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir);
} }
info->uses_frontface = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_FRONT_FACE); info->uses_frontface = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
info->uses_instanceid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID); info->uses_instanceid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
info->uses_base_vertex = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX); info->uses_base_vertex = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX);
info->uses_base_instance = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE); info->uses_base_instance = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE);
info->uses_invocationid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_INVOCATION_ID); info->uses_invocationid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INVOCATION_ID);
info->uses_grid_size = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_NUM_WORK_GROUPS); info->uses_grid_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_WORK_GROUPS);
info->uses_subgroup_info = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) || info->uses_subgroup_info = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) ||
nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_SUBGROUP_ID) || BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_ID) ||
nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_NUM_SUBGROUPS); BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_SUBGROUPS);
info->uses_variable_block_size = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_LOCAL_GROUP_SIZE); info->uses_variable_block_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_GROUP_SIZE);
info->uses_drawid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID); info->uses_drawid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
info->uses_primid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_PRIMITIVE_ID) || info->uses_primid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID; nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID;
info->reads_samplemask = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_MASK_IN); info->reads_samplemask = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
info->reads_tess_factors = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER) || info->reads_tess_factors = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_INNER) ||
nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER); BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_OUTER);
info->uses_linear_sample = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE); info->uses_linear_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
info->uses_linear_centroid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID); info->uses_linear_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
info->uses_linear_center = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL); info->uses_linear_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
info->uses_persp_sample = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE); info->uses_persp_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
info->uses_persp_centroid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID); info->uses_persp_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
info->uses_persp_center = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL); info->uses_persp_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
if (nir->info.stage == MESA_SHADER_FRAGMENT) { if (nir->info.stage == MESA_SHADER_FRAGMENT) {
info->writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH); info->writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH);
@@ -434,13 +434,12 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
info->uses_interp_at_sample || nir->info.writes_memory || info->uses_interp_at_sample || nir->info.writes_memory ||
nir->info.fs.uses_fbfetch_output || nir->info.fs.uses_fbfetch_output ||
nir->info.fs.needs_quad_helper_invocations || nir->info.fs.needs_quad_helper_invocations ||
(nir->info.system_values_read & BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
(BITFIELD64_BIT(SYSTEM_VALUE_FRAG_COORD) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_POINT_COORD) ||
BITFIELD64_BIT(SYSTEM_VALUE_POINT_COORD) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_ID) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) ||
BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_POS) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN) ||
BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_MASK_IN) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_HELPER_INVOCATION));
BITFIELD64_BIT(SYSTEM_VALUE_HELPER_INVOCATION))));
} }
/* Add color inputs to the list of inputs. */ /* Add color inputs to the list of inputs. */

4
src/gallium/frontends/lavapipe/lvp_pipeline.c
View File

@@ -792,8 +792,8 @@ lvp_graphics_pipeline_init(struct lvp_pipeline *pipeline,
if (pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]) { if (pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]) {
if (pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.fs.uses_sample_qualifier || if (pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.fs.uses_sample_qualifier ||
pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID | BITSET_TEST(pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
SYSTEM_BIT_SAMPLE_POS)) BITSET_TEST(pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS))
pipeline->force_min_sample = true; pipeline->force_min_sample = true;
} }
if (pipeline->pipeline_nir[MESA_SHADER_TESS_CTRL]) { if (pipeline->pipeline_nir[MESA_SHADER_TESS_CTRL]) {

12
src/intel/compiler/brw_fs.cpp
View File

@@ -8584,7 +8584,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
emit_shader_time_begin(); emit_shader_time_begin();
if (nir->info.inputs_read > 0 || if (nir->info.inputs_read > 0 ||
(nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) || BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
(nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) { (nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
if (devinfo->gen < 6) if (devinfo->gen < 6)
emit_interpolation_setup_gen4(); emit_interpolation_setup_gen4();
@@ -8965,7 +8965,7 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader,
struct brw_wm_prog_data *prog_data) struct brw_wm_prog_data *prog_data)
{ {
prog_data->uses_src_depth = prog_data->uses_src_w = prog_data->uses_src_depth = prog_data->uses_src_w =
shader->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_FRAG_COORD); BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD);
/* key->alpha_test_func means simulating alpha testing via discards, /* key->alpha_test_func means simulating alpha testing via discards,
* so the shader definitely kills pixels. * so the shader definitely kills pixels.
@@ -8981,14 +8981,14 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader,
prog_data->persample_dispatch = prog_data->persample_dispatch =
key->multisample_fbo && key->multisample_fbo &&
(key->persample_interp || (key->persample_interp ||
(shader->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID | BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
SYSTEM_BIT_SAMPLE_POS)) || BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) ||
shader->info.fs.uses_sample_qualifier || shader->info.fs.uses_sample_qualifier ||
shader->info.outputs_read); shader->info.outputs_read);
if (devinfo->gen >= 6) { if (devinfo->gen >= 6) {
prog_data->uses_sample_mask = prog_data->uses_sample_mask =
shader->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN; BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
/* From the Ivy Bridge PRM documentation for 3DSTATE_PS: /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
* *
@@ -9000,7 +9000,7 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader,
* persample dispatch, we hard-code it to 0.5. * persample dispatch, we hard-code it to 0.5.
*/ */
prog_data->uses_pos_offset = prog_data->persample_dispatch && prog_data->uses_pos_offset = prog_data->persample_dispatch &&
(shader->info.system_values_read & SYSTEM_BIT_SAMPLE_POS); BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS);
} }
prog_data->has_render_target_reads = shader->info.outputs_read != 0ull; prog_data->has_render_target_reads = shader->info.outputs_read != 0ull;

9
src/intel/compiler/brw_nir.c
View File

@@ -186,11 +186,10 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
* included here as it lives in its own vec4. * included here as it lives in its own vec4.
*/ */
const bool has_sgvs = const bool has_sgvs =
nir->info.system_values_read & BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FIRST_VERTEX) ||
(BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE) ||
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) ||
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
const unsigned num_inputs = util_bitcount64(nir->info.inputs_read); const unsigned num_inputs = util_bitcount64(nir->info.inputs_read);

32
src/intel/compiler/brw_vec4.cpp
View File

@@ -2876,43 +2876,35 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
/* gl_VertexID and gl_InstanceID are system values, but arrive via an /* gl_VertexID and gl_InstanceID are system values, but arrive via an
* incoming vertex attribute. So, add an extra slot. * incoming vertex attribute. So, add an extra slot.
*/ */
if (nir->info.system_values_read & if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FIRST_VERTEX) ||
(BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE) ||
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) ||
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID)) {
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) {
nr_attribute_slots++; nr_attribute_slots++;
} }
/* gl_DrawID and IsIndexedDraw share its very own vec4 */ /* gl_DrawID and IsIndexedDraw share its very own vec4 */
if (nir->info.system_values_read & if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID) ||
(BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) | BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_IS_INDEXED_DRAW)) {
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) {
nr_attribute_slots++; nr_attribute_slots++;
} }
if (nir->info.system_values_read & if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_IS_INDEXED_DRAW))
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))
prog_data->uses_is_indexed_draw = true; prog_data->uses_is_indexed_draw = true;
if (nir->info.system_values_read & if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FIRST_VERTEX))
BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX))
prog_data->uses_firstvertex = true; prog_data->uses_firstvertex = true;
if (nir->info.system_values_read & if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE))
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE))
prog_data->uses_baseinstance = true; prog_data->uses_baseinstance = true;
if (nir->info.system_values_read & if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
prog_data->uses_vertexid = true; prog_data->uses_vertexid = true;
if (nir->info.system_values_read & if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID))
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))
prog_data->uses_instanceid = true; prog_data->uses_instanceid = true;
if (nir->info.system_values_read & if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID))
BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID))
prog_data->uses_drawid = true; prog_data->uses_drawid = true;
/* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry

2
src/intel/compiler/brw_vec4_gs_visitor.cpp
View File

@@ -625,7 +625,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
nir->info.clip_distance_array_size; nir->info.clip_distance_array_size;
prog_data->include_primitive_id = prog_data->include_primitive_id =
(nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID)) != 0; BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
prog_data->invocations = nir->info.gs.invocations; prog_data->invocations = nir->info.gs.invocations;

2
src/intel/compiler/brw_vec4_tcs.cpp
View File

@@ -392,7 +392,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
brw_postprocess_nir(nir, compiler, is_scalar); brw_postprocess_nir(nir, compiler, is_scalar);
bool has_primitive_id = bool has_primitive_id =
nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID); BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
prog_data->patch_count_threshold = brw::get_patch_count_threshold(key->input_vertices); prog_data->patch_count_threshold = brw::get_patch_count_threshold(key->input_vertices);

2
src/mesa/drivers/dri/i965/brw_curbe.c
View File

@@ -332,7 +332,7 @@ emit:
* BRW_NEW_FRAGMENT_PROGRAM * BRW_NEW_FRAGMENT_PROGRAM
*/ */
if (devinfo->gen == 4 && !devinfo->is_g4x && if (devinfo->gen == 4 && !devinfo->is_g4x &&
(fp->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD))) { BITSET_TEST(fp->info.system_values_read, SYSTEM_VALUE_FRAG_COORD)) {
BEGIN_BATCH(2); BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2)); OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
OUT_BATCH(0); OUT_BATCH(0);

16
src/mesa/main/state.c
View File

@@ -174,14 +174,14 @@ _mesa_update_primitive_id_is_unused(struct gl_context *ctx)
* then the restriction on fragment shaders reading gl_PrimitiveID can be lifted. * then the restriction on fragment shaders reading gl_PrimitiveID can be lifted.
*/ */
ctx->_PrimitiveIDIsUnused = !( ctx->_PrimitiveIDIsUnused = !(
(tcs && (tcs->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_PRIMITIVE_ID) || (tcs && (BITSET_TEST(tcs->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
tcs->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)) || tcs->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)) ||
(tes && (tes->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_PRIMITIVE_ID) || (tes && (BITSET_TEST(tes->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
tes->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)) || tes->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)) ||
(gs && (gs->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_PRIMITIVE_ID) || (gs && (BITSET_TEST(gs->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
gs->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)) || gs->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)) ||
(fs && (fs->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_PRIMITIVE_ID) || (fs && (BITSET_TEST(fs->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
fs->info.inputs_read & VARYING_BIT_PRIMITIVE_ID))); fs->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)));
} }

6
src/mesa/program/prog_to_nir.c
View File

@@ -904,10 +904,8 @@ setup_registers_and_variables(struct ptn_compile *c)
} }
/* Create system value variables */ /* Create system value variables */
uint64_t system_values_read = c->prog->info.system_values_read; int i;
while (system_values_read) { BITSET_FOREACH_SET(i, c->prog->info.system_values_read, SYSTEM_VALUE_MAX) {
const int i = u_bit_scan64(&system_values_read);
nir_variable *var = nir_variable *var =
nir_variable_create(shader, nir_var_system_value, glsl_vec4_type(), nir_variable_create(shader, nir_var_system_value, glsl_vec4_type(),
ralloc_asprintf(shader, "sv_%d", i)); ralloc_asprintf(shader, "sv_%d", i));

4
src/mesa/program/program.c
View File

@@ -524,8 +524,8 @@ _mesa_get_min_invocations_per_fragment(struct gl_context *ctx,
* forces per-sample shading" * forces per-sample shading"
*/ */
if (prog->info.fs.uses_sample_qualifier || if (prog->info.fs.uses_sample_qualifier ||
(prog->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID | BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
SYSTEM_BIT_SAMPLE_POS))) BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS))
return MAX2(_mesa_geometric_samples(ctx->DrawBuffer), 1); return MAX2(_mesa_geometric_samples(ctx->DrawBuffer), 1);
else if (ctx->Multisample.SampleShading) else if (ctx->Multisample.SampleShading)
return MAX2(ceilf(ctx->Multisample.MinSampleShadingValue * return MAX2(ceilf(ctx->Multisample.MinSampleShadingValue *

2
src/mesa/program/programopt.c
View File

@@ -597,7 +597,7 @@ _mesa_program_fragment_position_to_sysval(struct gl_program *prog)
return; return;
prog->info.inputs_read &= ~BITFIELD64_BIT(VARYING_SLOT_POS); prog->info.inputs_read &= ~BITFIELD64_BIT(VARYING_SLOT_POS);
prog->info.system_values_read |= 1 << SYSTEM_VALUE_FRAG_COORD; BITSET_SET(prog->info.system_values_read, SYSTEM_VALUE_FRAG_COORD);
for (i = 0; i < prog->arb.NumInstructions; i++) { for (i = 0; i < prog->arb.NumInstructions; i++) {
struct prog_instruction *inst = prog->arb.Instructions + i; struct prog_instruction *inst = prog->arb.Instructions + i;

74
src/mesa/state_tracker/st_glsl_to_tgsi.cpp
View File

@@ -6886,49 +6886,41 @@ st_translate_program(
/* Declare misc input registers /* Declare misc input registers
*/ */
{ BITSET_FOREACH_SET(i, proginfo->info.system_values_read, SYSTEM_VALUE_MAX) {
GLbitfield64 sysInputs = proginfo->info.system_values_read; enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
for (i = 0; sysInputs; i++) { t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
if (sysInputs & (1ull << i)) {
enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0); if (semName == TGSI_SEMANTIC_INSTANCEID ||
semName == TGSI_SEMANTIC_VERTEXID) {
if (semName == TGSI_SEMANTIC_INSTANCEID || /* From Gallium perspective, these system values are always
semName == TGSI_SEMANTIC_VERTEXID) { * integer, and require native integer support. However, if
/* From Gallium perspective, these system values are always * native integer is supported on the vertex stage but not the
* integer, and require native integer support. However, if * pixel stage (e.g, i915g + draw), Mesa will generate IR that
* native integer is supported on the vertex stage but not the * assumes these system values are floats. To resolve the
* pixel stage (e.g, i915g + draw), Mesa will generate IR that * inconsistency, we insert a U2F.
* assumes these system values are floats. To resolve the */
* inconsistency, we insert a U2F. struct st_context *st = st_context(ctx);
*/ struct pipe_screen *pscreen = st->screen;
struct st_context *st = st_context(ctx); assert(procType == PIPE_SHADER_VERTEX);
struct pipe_screen *pscreen = st->screen; assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
assert(procType == PIPE_SHADER_VERTEX); (void) pscreen;
assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS)); if (!ctx->Const.NativeIntegers) {
(void) pscreen; struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
if (!ctx->Const.NativeIntegers) { ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg); t->systemValues[i]);
ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
t->systemValues[i]);
t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
}
}
if (procType == PIPE_SHADER_FRAGMENT &&
semName == TGSI_SEMANTIC_POSITION)
emit_wpos(st_context(ctx), t, proginfo, ureg,
program->wpos_transform_const);
if (procType == PIPE_SHADER_FRAGMENT &&
semName == TGSI_SEMANTIC_SAMPLEPOS)
emit_samplepos_adjustment(t, program->wpos_transform_const);
sysInputs &= ~(1ull << i);
} }
} }
if (procType == PIPE_SHADER_FRAGMENT &&
semName == TGSI_SEMANTIC_POSITION)
emit_wpos(st_context(ctx), t, proginfo, ureg,
program->wpos_transform_const);
if (procType == PIPE_SHADER_FRAGMENT &&
semName == TGSI_SEMANTIC_SAMPLEPOS)
emit_samplepos_adjustment(t, program->wpos_transform_const);
} }
t->array_sizes = program->array_sizes; t->array_sizes = program->array_sizes;
@@ -7231,8 +7223,8 @@ get_mesa_program_tgsi(struct gl_context *ctx,
/* This must be done before the uniform storage is associated. */ /* This must be done before the uniform storage is associated. */
if (shader->Stage == MESA_SHADER_FRAGMENT && if (shader->Stage == MESA_SHADER_FRAGMENT &&
(prog->info.inputs_read & VARYING_BIT_POS || (prog->info.inputs_read & VARYING_BIT_POS ||
prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) || BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) { BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS))) {
static const gl_state_index16 wposTransformState[STATE_LENGTH] = { static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
STATE_FB_WPOS_Y_TRANSFORM STATE_FB_WPOS_Y_TRANSFORM
}; };

2
src/microsoft/compiler/nir_to_dxil.c
View File

@@ -4214,7 +4214,7 @@ allocate_sysvalues(struct ntd_context *ctx, nir_shader *s)
for (unsigned i = 0; i < ARRAY_SIZE(possible_sysvalues); ++i) { for (unsigned i = 0; i < ARRAY_SIZE(possible_sysvalues); ++i) {
struct sysvalue_name *info = &possible_sysvalues[i]; struct sysvalue_name *info = &possible_sysvalues[i];
if ((1 << info->value) & s->info.system_values_read) { if (BITSET_TEST(s->info.system_values_read, info->value)) {
if (!append_input_or_sysvalue(ctx, s, info->slot, if (!append_input_or_sysvalue(ctx, s, info->slot,
info->value, info->name, info->value, info->name,
driver_location++)) driver_location++))