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nir,amd: add and use nir_intrinsic_load_esgs_vertex_stride_amd

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This will emulate VGT_ESGS_RING_ITEMSIZE, which does the multiplication
for us. It's beneficial to stop setting VGT_ESGS_RING_ITEMSIZE to reduce
context rolls, and also the register will be removed in the future.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
This commit is contained in:
Marek Olšák
2023-02-20 00:50:24 -05:00
committed by Marge Bot
parent 5e837f9594
commit 9f1e6d8f70
5 changed files with 13 additions and 0 deletions
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2
src/amd/common/ac_nir_lower_esgs_io_to_mem.c
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@@ -269,6 +269,8 @@ gs_per_vertex_input_offset(nir_builder *b,
? gs_per_vertex_input_vertex_offset_gfx9(b, st, vertex_src)
: gs_per_vertex_input_vertex_offset_gfx6(b, st, vertex_src);
vertex_offset = nir_imul(b, vertex_offset, nir_load_esgs_vertex_stride_amd(b));
unsigned base_stride = st->gfx_level >= GFX9 ? 1 : 64 /* Wave size on GFX6-8 */;
nir_ssa_def *io_off = ac_nir_calc_io_offset(b, instr, nir_imm_int(b, base_stride * 4u), base_stride, st->map_io);
nir_ssa_def *off = nir_iadd(b, io_off, vertex_offset);

4
src/amd/vulkan/radv_nir_lower_abi.c
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@@ -281,6 +281,10 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
replacement = nir_imm_int(b, io_num * 16);
break;
}
case nir_intrinsic_load_esgs_vertex_stride_amd:
/* TODO: pass the value of VGT_ESGS_RING_ITEMSIZE here and set the register to 1. */
replacement = nir_imm_int(b, 1);
break;
case nir_intrinsic_load_hs_out_patch_data_offset_amd: {
unsigned out_vertices_per_patch = b->shader->info.tess.tcs_vertices_out;
unsigned num_tcs_outputs = stage == MESA_SHADER_TESS_CTRL ?

1
src/compiler/nir/nir_divergence_analysis.c
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@@ -196,6 +196,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_mesh_inline_data_intel:
case nir_intrinsic_load_ray_num_dss_rt_stacks_intel:
case nir_intrinsic_load_lshs_vertex_stride_amd:
case nir_intrinsic_load_esgs_vertex_stride_amd:
case nir_intrinsic_load_hs_out_patch_data_offset_amd:
case nir_intrinsic_load_clip_half_line_width_amd:
case nir_intrinsic_load_num_vertices_per_primitive_amd:

3
src/compiler/nir/nir_intrinsics.py
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@@ -1509,6 +1509,9 @@ intrinsic("store_shared2_amd", [2, 1], indices=[OFFSET0, OFFSET1, ST64])
# Vertex stride in LS-HS buffer
system_value("lshs_vertex_stride_amd", 1)
# Vertex stride in ES-GS buffer
system_value("esgs_vertex_stride_amd", 1)
# Per patch data offset in HS VRAM output buffer
system_value("hs_out_patch_data_offset_amd", 1)

3
src/gallium/drivers/radeonsi/si_nir_lower_abi.c
View File

@@ -179,6 +179,9 @@ static bool lower_abi_instr(nir_builder *b, nir_instr *instr, struct lower_abi_s
else
unreachable("no nir_load_lshs_vertex_stride_amd");
break;
case nir_intrinsic_load_esgs_vertex_stride_amd:
replacement = nir_imm_int(b, 1);
break;
case nir_intrinsic_load_tcs_num_patches_amd: {
nir_ssa_def *tmp = ac_nir_unpack_arg(b, &args->ac, args->tcs_offchip_layout, 0, 6);
replacement = nir_iadd_imm(b, tmp, 1);