iris: implement another workaround for non pipelined states
v2: add comment (Ken) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
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@@ -387,6 +387,8 @@ emit_state(struct iris_batch *batch,
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static void
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flush_before_state_base_change(struct iris_batch *batch)
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{
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const struct gen_device_info *devinfo = &batch->screen->devinfo;
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/* Flush before emitting STATE_BASE_ADDRESS.
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*
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* This isn't documented anywhere in the PRM. However, it seems to be
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@@ -412,7 +414,18 @@ flush_before_state_base_change(struct iris_batch *batch)
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"change STATE_BASE_ADDRESS (flushes)",
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PIPE_CONTROL_RENDER_TARGET_FLUSH |
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PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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PIPE_CONTROL_DATA_CACHE_FLUSH);
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PIPE_CONTROL_DATA_CACHE_FLUSH |
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/* GEN:BUG:1606662791:
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*
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* Software must program PIPE_CONTROL command
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* with "HDC Pipeline Flush" prior to
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* programming of the below two non-pipeline
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* state :
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* * STATE_BASE_ADDRESS
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* * 3DSTATE_BINDING_TABLE_POOL_ALLOC
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*/
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((GEN_GEN == 12 && devinfo->revision == 0 /* A0 */ ?
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PIPE_CONTROL_FLUSH_HDC : 0)));
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}
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static void
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