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intel/compiler: Create and use struct for Bindless thread payload

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Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
This commit is contained in:
Caio Oliveira
2022-08-25 17:00:15 -07:00
committed by Marge Bot
parent a70378f292
commit 9de790760e
4 changed files with 41 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/intel/compiler/brw_fs.cpp
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@@ -6837,8 +6837,7 @@ fs_visitor::run_bs(bool allow_spilling)
{
assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
/* R0: thread header, R1: stack IDs, R2: argument addresses */
payload().num_regs = 3;
payload_ = new bs_thread_payload();
emit_nir_code();

14
src/intel/compiler/brw_fs.h
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@@ -154,6 +154,15 @@ struct task_mesh_thread_payload : public thread_payload {
fs_reg task_urb_input;
};
struct bs_thread_payload : public thread_payload {
bs_thread_payload();
fs_reg global_arg_ptr;
fs_reg local_arg_ptr;
void load_shader_type(const brw::fs_builder &bld, fs_reg &dest) const;
};
/**
* The fragment shader front-end.
*
@@ -493,6 +502,11 @@ public:
return *static_cast<task_mesh_thread_payload *>(this->payload_);
}
bs_thread_payload &bs_payload() {
assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
return *static_cast<bs_thread_payload *>(this->payload_);
}
bool source_depth_to_render_target;
bool runtime_check_aads_emit;

12
src/intel/compiler/brw_fs_nir.cpp
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@@ -3956,6 +3956,7 @@ fs_visitor::nir_emit_bs_intrinsic(const fs_builder &bld,
nir_intrinsic_instr *instr)
{
assert(brw_shader_stage_is_bindless(stage));
const bs_thread_payload &payload = bs_payload();
fs_reg dest;
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
@@ -3963,19 +3964,16 @@ fs_visitor::nir_emit_bs_intrinsic(const fs_builder &bld,
switch (instr->intrinsic) {
case nir_intrinsic_load_btd_global_arg_addr_intel:
bld.MOV(dest, retype(brw_vec1_grf(2, 0), dest.type));
bld.MOV(dest, retype(payload.global_arg_ptr, dest.type));
break;
case nir_intrinsic_load_btd_local_arg_addr_intel:
bld.MOV(dest, retype(brw_vec1_grf(2, 2), dest.type));
bld.MOV(dest, retype(payload.local_arg_ptr, dest.type));
break;
case nir_intrinsic_load_btd_shader_type_intel: {
fs_reg ud_dest = retype(dest, BRW_REGISTER_TYPE_UD);
bld.MOV(ud_dest, retype(brw_vec1_grf(0, 3), ud_dest.type));
bld.AND(ud_dest, ud_dest, brw_imm_ud(0xf));
case nir_intrinsic_load_btd_shader_type_intel:
payload.load_shader_type(bld, dest);
break;
}
default:
nir_emit_intrinsic(bld, instr);

21
src/intel/compiler/brw_fs_thread_payload.cpp
View File

@@ -405,3 +405,24 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v)
num_regs = r;
}
bs_thread_payload::bs_thread_payload()
{
/* R0: Thread header. */
/* R1: Stack IDs. */
/* R2: Argument addresses. */
global_arg_ptr = retype(brw_vec1_grf(2, 0), BRW_REGISTER_TYPE_UD);
local_arg_ptr = retype(brw_vec1_grf(2, 2), BRW_REGISTER_TYPE_UD);
num_regs = 3;
}
void
bs_thread_payload::load_shader_type(const fs_builder &bld, fs_reg &dest) const
{
fs_reg ud_dest = retype(dest, BRW_REGISTER_TYPE_UD);
bld.MOV(ud_dest, retype(brw_vec1_grf(0, 3), ud_dest.type));
bld.AND(ud_dest, ud_dest, brw_imm_ud(0xf));
}