anv: Remove block promoting non CPU mapped bos to coherent
The intention of this block was to set one of the flags that is used
to select a PAT index but this was doing more than that.
It was promoting WB+0 way coherency BOs to WC+1 way coherency possibly
causing regression in platforms without LLC.
anv_device_get_pat_entry() return WC/writecombining if no flags is
set so we don't need this block after all.
Reported-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Fixes: a65e982b44
("anv: Split ANV_BO_ALLOC_HOST_CACHED_COHERENT into two actual flags")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29769>
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@@ -1575,12 +1575,6 @@ anv_device_alloc_bo(struct anv_device *device,
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assert((alloc_flags & ANV_BO_ALLOC_MAPPED) == 0 ||
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(alloc_flags & (ANV_BO_ALLOC_HOST_CACHED | ANV_BO_ALLOC_HOST_COHERENT)));
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/* KMD requires a valid PAT index, so setting HOST_COHERENT/WC to bos that
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* don't need CPU access
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*/
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if ((alloc_flags & ANV_BO_ALLOC_MAPPED) == 0)
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alloc_flags |= ANV_BO_ALLOC_HOST_COHERENT;
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/* In platforms with LLC we can promote all bos to cached+coherent for free */
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const enum anv_bo_alloc_flags not_allowed_promotion = ANV_BO_ALLOC_SCANOUT |
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ANV_BO_ALLOC_EXTERNAL |
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