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i965/fs: Use align1 mode on ternary instructions on Gen10+

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Align1 mode offers some nice features over align16, like access to more
data types and the ability to use a 16-bit immediate. This patch does
not start using any new features. It just emits ternary instructions in
align1 mode.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
This commit is contained in:
Matt Turner
2017-06-14 14:48:11 -07:00
parent 8c16c9c677
commit 9cd60fce9c
1 changed files with 8 additions and 4 deletions
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4
src/intel/compiler/brw_fs_generator.cpp
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@@ -1729,12 +1729,14 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
case BRW_OPCODE_MAD:
assert(devinfo->gen >= 6);
if (devinfo->gen < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MAD(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_LRP:
assert(devinfo->gen >= 6);
if (devinfo->gen < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_LRP(p, dst, src[0], src[1], src[2]);
break;
@@ -1833,6 +1835,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
case BRW_OPCODE_BFE:
assert(devinfo->gen >= 7);
if (devinfo->gen < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_BFE(p, dst, src[0], src[1], src[2]);
break;
@@ -1843,6 +1846,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
break;
case BRW_OPCODE_BFI2:
assert(devinfo->gen >= 7);
if (devinfo->gen < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_BFI2(p, dst, src[0], src[1], src[2]);
break;