intel/fs/validate: Assert SEND [extended] descriptors are uniform
This is required by code-gen since it generates a 1-wide OR and it'll blow up if the register width > 1. It's also way better than the "your register is the wrong size" assert you get from the more generic validation check. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
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9c658b1fc8
@@ -87,7 +87,8 @@ fs_visitor::validate()
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{
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#ifndef NDEBUG
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foreach_block_and_inst (block, fs_inst, inst, cfg) {
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if (inst->opcode == SHADER_OPCODE_URB_WRITE_LOGICAL) {
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switch (inst->opcode) {
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case SHADER_OPCODE_URB_WRITE_LOGICAL: {
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const unsigned header_size = 1 +
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unsigned(inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE) +
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unsigned(inst->src[URB_LOGICAL_SRC_CHANNEL_MASK].file != BAD_FILE);
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@@ -99,6 +100,15 @@ fs_visitor::validate()
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}
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fsv_assert_eq(header_size + data_size, inst->mlen);
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break;
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}
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case SHADER_OPCODE_SEND:
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fsv_assert(is_uniform(inst->src[0]) && is_uniform(inst->src[1]));
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break;
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default:
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break;
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}
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if (inst->is_3src(compiler)) {
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@@ -370,6 +370,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
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desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
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ubld.AND(desc, dynamic_msaa_flags(prog_data),
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brw_imm_ud(BRW_WM_MSAA_FLAG_COARSE_DISPATCH));
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desc = component(desc, 0);
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}
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uint32_t ex_desc = 0;
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