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radeon/vcn2: enable rate control for hevc encoding

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Based on b0626c1f30 ("radeon/vcn: enable rate control for hevc encoding").

Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2225
Fixes: 587b9c5dae ("radeon/vcn: implement vcn 2.0 encode")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
2019-12-17 10:41:39 +01:00
parent 02dd1fb859
commit 9c2a3b4e75
1 changed files with 7 additions and 1 deletions
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8
src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
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@@ -196,7 +196,13 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
radeon_enc_code_se(enc, 0x0); radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1); radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1); radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1); if (enc->enc_pic.rc_session_init.rate_control_method ==
RENCODE_RATE_CONTROL_METHOD_NONE)
radeon_enc_code_fixed_bits(enc, 0x0, 1);
else {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, 0x0);
}
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_enc_code_fixed_bits(enc, 0x0, 1); radeon_enc_code_fixed_bits(enc, 0x0, 1);