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intel: drop likely/unlikely around INTEL_DEBUG

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It's included in declaration of INTEL_DEBUG.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6732>
This commit is contained in:
Marcin Ślusarz
2020-09-14 18:53:41 +02:00
committed by Marge Bot
parent e06da554e9
commit 9c25689287
10 changed files with 32 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/compiler/brw_compile_clip.c
View File

@@ -85,7 +85,7 @@ brw_compile_clip(const struct brw_compiler *compiler,
const unsigned *program = brw_get_program(&c.func, final_assembly_size); const unsigned *program = brw_get_program(&c.func, final_assembly_size);
if (unlikely(INTEL_DEBUG & DEBUG_CLIP)) { if (INTEL_DEBUG & DEBUG_CLIP) {
fprintf(stderr, "clip:\n"); fprintf(stderr, "clip:\n");
brw_disassemble_with_labels(compiler->devinfo, brw_disassemble_with_labels(compiler->devinfo,
program, 0, *final_assembly_size, stderr); program, 0, *final_assembly_size, stderr);

2
src/intel/compiler/brw_compile_sf.c
View File

@@ -868,7 +868,7 @@ brw_compile_sf(const struct brw_compiler *compiler,
const unsigned *program = brw_get_program(&c.func, final_assembly_size); const unsigned *program = brw_get_program(&c.func, final_assembly_size);
if (unlikely(INTEL_DEBUG & DEBUG_SF)) { if (INTEL_DEBUG & DEBUG_SF) {
fprintf(stderr, "sf:\n"); fprintf(stderr, "sf:\n");
brw_disassemble_with_labels(compiler->devinfo, brw_disassemble_with_labels(compiler->devinfo,
program, 0, *final_assembly_size, stderr); program, 0, *final_assembly_size, stderr);

2
src/intel/compiler/brw_eu_compact.c
View File

@@ -2270,7 +2270,7 @@ void
brw_compact_instructions(struct brw_codegen *p, int start_offset, brw_compact_instructions(struct brw_codegen *p, int start_offset,
struct disasm_info *disasm) struct disasm_info *disasm)
{ {
if (unlikely(INTEL_DEBUG & DEBUG_NO_COMPACTION)) if (INTEL_DEBUG & DEBUG_NO_COMPACTION)
return; return;
const struct gen_device_info *devinfo = p->devinfo; const struct gen_device_info *devinfo = p->devinfo;

20
src/intel/compiler/brw_fs.cpp
View File

@@ -7408,7 +7408,7 @@ fs_visitor::optimize()
pass_num++; \ pass_num++; \
bool this_progress = pass(args); \ bool this_progress = pass(args); \
\ \
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \ if ((INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
char filename[64]; \ char filename[64]; \
snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \ snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \ stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
@@ -7422,7 +7422,7 @@ fs_visitor::optimize()
this_progress; \ this_progress; \
}) })
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) { if (INTEL_DEBUG & DEBUG_OPTIMIZER) {
char filename[64]; char filename[64];
snprintf(filename, 64, "%s%d-%s-00-00-start", snprintf(filename, 64, "%s%d-%s-00-00-start",
stage_abbrev, dispatch_width, nir->info.name); stage_abbrev, dispatch_width, nir->info.name);
@@ -8632,7 +8632,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
delete v8; delete v8;
return NULL; return NULL;
} else if (likely(!(INTEL_DEBUG & DEBUG_NO8))) { } else if (!(INTEL_DEBUG & DEBUG_NO8)) {
simd8_cfg = v8->cfg; simd8_cfg = v8->cfg;
prog_data->base.dispatch_grf_start_reg = v8->payload.num_regs; prog_data->base.dispatch_grf_start_reg = v8->payload.num_regs;
prog_data->reg_blocks_8 = brw_register_blocks(v8->grf_used); prog_data->reg_blocks_8 = brw_register_blocks(v8->grf_used);
@@ -8654,7 +8654,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
if (!has_spilled && if (!has_spilled &&
v8->max_dispatch_width >= 16 && v8->max_dispatch_width >= 16 &&
likely(!(INTEL_DEBUG & DEBUG_NO16) || use_rep_send)) { (!(INTEL_DEBUG & DEBUG_NO16) || use_rep_send)) {
/* Try a SIMD16 compile */ /* Try a SIMD16 compile */
v16 = new fs_visitor(compiler, log_data, mem_ctx, &key->base, v16 = new fs_visitor(compiler, log_data, mem_ctx, &key->base,
&prog_data->base, nir, 16, shader_time_index16); &prog_data->base, nir, 16, shader_time_index16);
@@ -8760,7 +8760,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
fs_generator g(compiler, log_data, mem_ctx, &prog_data->base, fs_generator g(compiler, log_data, mem_ctx, &prog_data->base,
v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT); v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT);
if (unlikely(INTEL_DEBUG & DEBUG_WM)) { if (INTEL_DEBUG & DEBUG_WM) {
g.enable_debug(ralloc_asprintf(mem_ctx, "%s fragment shader %s", g.enable_debug(ralloc_asprintf(mem_ctx, "%s fragment shader %s",
nir->info.label ? nir->info.label ?
nir->info.label : "unnamed", nir->info.label : "unnamed",
@@ -9008,7 +9008,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
fs_visitor *v8 = NULL, *v16 = NULL, *v32 = NULL; fs_visitor *v8 = NULL, *v16 = NULL, *v32 = NULL;
fs_visitor *v = NULL; fs_visitor *v = NULL;
if (likely(!(INTEL_DEBUG & DEBUG_NO8)) && if (!(INTEL_DEBUG & DEBUG_NO8) &&
min_dispatch_width <= 8 && max_dispatch_width >= 8) { min_dispatch_width <= 8 && max_dispatch_width >= 8) {
nir_shader *nir8 = compile_cs_to_nir(compiler, mem_ctx, key, nir_shader *nir8 = compile_cs_to_nir(compiler, mem_ctx, key,
nir, 8); nir, 8);
@@ -9032,7 +9032,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
cs_fill_push_const_info(compiler->devinfo, prog_data); cs_fill_push_const_info(compiler->devinfo, prog_data);
} }
if (likely(!(INTEL_DEBUG & DEBUG_NO16)) && if (!(INTEL_DEBUG & DEBUG_NO16) &&
(generate_all || !prog_data->prog_spilled) && (generate_all || !prog_data->prog_spilled) &&
min_dispatch_width <= 16 && max_dispatch_width >= 16) { min_dispatch_width <= 16 && max_dispatch_width >= 16) {
/* Try a SIMD16 compile */ /* Try a SIMD16 compile */
@@ -9079,7 +9079,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
(INTEL_DEBUG & DEBUG_DO32) || (INTEL_DEBUG & DEBUG_DO32) ||
generate_all; generate_all;
if (likely(!(INTEL_DEBUG & DEBUG_NO32)) && if (!(INTEL_DEBUG & DEBUG_NO32) &&
(generate_all || !prog_data->prog_spilled) && (generate_all || !prog_data->prog_spilled) &&
needs_32 && needs_32 &&
min_dispatch_width <= 32 && max_dispatch_width >= 32) { min_dispatch_width <= 32 && max_dispatch_width >= 32) {
@@ -9119,7 +9119,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
} }
} }
if (unlikely(!v && (INTEL_DEBUG & (DEBUG_NO8 | DEBUG_NO16 | DEBUG_NO32)))) { if (unlikely(!v) && (INTEL_DEBUG & (DEBUG_NO8 | DEBUG_NO16 | DEBUG_NO32))) {
if (error_str) { if (error_str) {
*error_str = *error_str =
ralloc_strdup(mem_ctx, ralloc_strdup(mem_ctx,
@@ -9198,7 +9198,7 @@ brw_cs_simd_size_for_group_size(const struct gen_device_info *devinfo,
static const unsigned simd16 = 1 << 1; static const unsigned simd16 = 1 << 1;
static const unsigned simd32 = 1 << 2; static const unsigned simd32 = 1 << 2;
if (unlikely(INTEL_DEBUG & DEBUG_DO32) && (mask & simd32)) if ((INTEL_DEBUG & DEBUG_DO32) && (mask & simd32))
return 32; return 32;
/* Limit max_threads to 64 for the GPGPU_WALKER command */ /* Limit max_threads to 64 for the GPGPU_WALKER command */

10
src/intel/compiler/brw_shader.cpp
View File

@@ -1219,14 +1219,14 @@ backend_shader::dump_instructions(const char *name) const
if (cfg) { if (cfg) {
int ip = 0; int ip = 0;
foreach_block_and_inst(block, backend_instruction, inst, cfg) { foreach_block_and_inst(block, backend_instruction, inst, cfg) {
if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) if (!(INTEL_DEBUG & DEBUG_OPTIMIZER))
fprintf(file, "%4d: ", ip++); fprintf(file, "%4d: ", ip++);
dump_instruction(inst, file); dump_instruction(inst, file);
} }
} else { } else {
int ip = 0; int ip = 0;
foreach_in_list(backend_instruction, inst, &instructions) { foreach_in_list(backend_instruction, inst, &instructions) {
if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) if (!(INTEL_DEBUG & DEBUG_OPTIMIZER))
fprintf(file, "%4d: ", ip++); fprintf(file, "%4d: ", ip++);
dump_instruction(inst, file); dump_instruction(inst, file);
} }
@@ -1340,7 +1340,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
: BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW; : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
} }
if (unlikely(INTEL_DEBUG & DEBUG_TES)) { if (INTEL_DEBUG & DEBUG_TES) {
fprintf(stderr, "TES Input "); fprintf(stderr, "TES Input ");
brw_print_vue_map(stderr, input_vue_map); brw_print_vue_map(stderr, input_vue_map);
fprintf(stderr, "TES Output "); fprintf(stderr, "TES Output ");
@@ -1362,7 +1362,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
fs_generator g(compiler, log_data, mem_ctx, fs_generator g(compiler, log_data, mem_ctx,
&prog_data->base.base, false, MESA_SHADER_TESS_EVAL); &prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
if (unlikely(INTEL_DEBUG & DEBUG_TES)) { if (INTEL_DEBUG & DEBUG_TES) {
g.enable_debug(ralloc_asprintf(mem_ctx, g.enable_debug(ralloc_asprintf(mem_ctx,
"%s tessellation evaluation shader %s", "%s tessellation evaluation shader %s",
nir->info.label ? nir->info.label nir->info.label ? nir->info.label
@@ -1385,7 +1385,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
return NULL; return NULL;
} }
if (unlikely(INTEL_DEBUG & DEBUG_TES)) if (INTEL_DEBUG & DEBUG_TES)
v.dump_instructions(); v.dump_instructions();
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir, assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,

6
src/intel/compiler/brw_vec4.cpp
View File

@@ -2685,7 +2685,7 @@ vec4_visitor::run()
pass_num++; \ pass_num++; \
bool this_progress = pass(args); \ bool this_progress = pass(args); \
\ \
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \ if ((INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
char filename[64]; \ char filename[64]; \
snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \ snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
stage_abbrev, nir->info.name, iteration, pass_num); \ stage_abbrev, nir->info.name, iteration, pass_num); \
@@ -2698,7 +2698,7 @@ vec4_visitor::run()
}) })
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) { if (INTEL_DEBUG & DEBUG_OPTIMIZER) {
char filename[64]; char filename[64];
snprintf(filename, 64, "%s-%s-00-00-start", snprintf(filename, 64, "%s-%s-00-00-start",
stage_abbrev, nir->info.name); stage_abbrev, nir->info.name);
@@ -2761,7 +2761,7 @@ vec4_visitor::run()
setup_payload(); setup_payload();
if (unlikely(INTEL_DEBUG & DEBUG_SPILL_VEC4)) { if (INTEL_DEBUG & DEBUG_SPILL_VEC4) {
/* Debug of register spilling: Go spill everything. */ /* Debug of register spilling: Go spill everything. */
const int grf_count = alloc.count; const int grf_count = alloc.count;
float spill_costs[alloc.count]; float spill_costs[alloc.count];

6
src/intel/compiler/brw_vec4_gs_visitor.cpp
View File

@@ -813,7 +813,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
/* Now that prog_data setup is done, we are ready to actually compile the /* Now that prog_data setup is done, we are ready to actually compile the
* program. * program.
*/ */
if (unlikely(INTEL_DEBUG & DEBUG_GS)) { if (INTEL_DEBUG & DEBUG_GS) {
fprintf(stderr, "GS Input "); fprintf(stderr, "GS Input ");
brw_print_vue_map(stderr, &c.input_vue_map); brw_print_vue_map(stderr, &c.input_vue_map);
fprintf(stderr, "GS Output "); fprintf(stderr, "GS Output ");
@@ -829,7 +829,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
fs_generator g(compiler, log_data, mem_ctx, fs_generator g(compiler, log_data, mem_ctx,
&prog_data->base.base, false, MESA_SHADER_GEOMETRY); &prog_data->base.base, false, MESA_SHADER_GEOMETRY);
if (unlikely(INTEL_DEBUG & DEBUG_GS)) { if (INTEL_DEBUG & DEBUG_GS) {
const char *label = const char *label =
nir->info.label ? nir->info.label : "unnamed"; nir->info.label ? nir->info.label : "unnamed";
char *name = ralloc_asprintf(mem_ctx, "%s geometry shader %s", char *name = ralloc_asprintf(mem_ctx, "%s geometry shader %s",
@@ -854,7 +854,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
* dual object mode. * dual object mode.
*/ */
if (prog_data->invocations <= 1 && if (prog_data->invocations <= 1 &&
likely(!(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS))) { !(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS)) {
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
brw::vec4_gs_visitor v(compiler, log_data, &c, prog_data, nir, brw::vec4_gs_visitor v(compiler, log_data, &c, prog_data, nir,

8
src/intel/compiler/brw_vec4_tcs.cpp
View File

@@ -143,7 +143,7 @@ vec4_tcs_visitor::emit_thread_end()
emit(BRW_OPCODE_ENDIF); emit(BRW_OPCODE_ENDIF);
} }
if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME)) if (INTEL_DEBUG & DEBUG_SHADER_TIME)
emit_shader_time_end(); emit_shader_time_end();
inst = emit(TCS_OPCODE_THREAD_END); inst = emit(TCS_OPCODE_THREAD_END);
@@ -453,7 +453,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
*/ */
vue_prog_data->urb_read_length = 0; vue_prog_data->urb_read_length = 0;
if (unlikely(INTEL_DEBUG & DEBUG_TCS)) { if (INTEL_DEBUG & DEBUG_TCS) {
fprintf(stderr, "TCS Input "); fprintf(stderr, "TCS Input ");
brw_print_vue_map(stderr, &input_vue_map); brw_print_vue_map(stderr, &input_vue_map);
fprintf(stderr, "TCS Output "); fprintf(stderr, "TCS Output ");
@@ -474,7 +474,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
fs_generator g(compiler, log_data, mem_ctx, fs_generator g(compiler, log_data, mem_ctx,
&prog_data->base.base, false, MESA_SHADER_TESS_CTRL); &prog_data->base.base, false, MESA_SHADER_TESS_CTRL);
if (unlikely(INTEL_DEBUG & DEBUG_TCS)) { if (INTEL_DEBUG & DEBUG_TCS) {
g.enable_debug(ralloc_asprintf(mem_ctx, g.enable_debug(ralloc_asprintf(mem_ctx,
"%s tessellation control shader %s", "%s tessellation control shader %s",
nir->info.label ? nir->info.label nir->info.label ? nir->info.label
@@ -497,7 +497,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
return NULL; return NULL;
} }
if (unlikely(INTEL_DEBUG & DEBUG_TCS)) if (INTEL_DEBUG & DEBUG_TCS)
v.dump_instructions(); v.dump_instructions();

2
src/intel/dev/gen_debug.h
View File

@@ -118,7 +118,7 @@ extern uint64_t intel_debug;
#endif /* HAVE_ANDROID_PLATFORM */ #endif /* HAVE_ANDROID_PLATFORM */
#define DBG(...) do { \ #define DBG(...) do { \
if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG)) \ if (INTEL_DEBUG & FILE_DEBUG_FLAG) \
dbg_printf(__VA_ARGS__); \ dbg_printf(__VA_ARGS__); \
} while(0) } while(0)

6
src/intel/perf/gen_perf.c
View File

@@ -80,7 +80,7 @@ get_sysfs_dev_dir(struct gen_perf_config *perf, int fd)
perf->sysfs_dev_dir[0] = '\0'; perf->sysfs_dev_dir[0] = '\0';
if (unlikely(INTEL_DEBUG & DEBUG_NO_OACONFIG)) if (INTEL_DEBUG & DEBUG_NO_OACONFIG)
return true; return true;
if (fstat(fd, &sb)) { if (fstat(fd, &sb)) {
@@ -407,7 +407,7 @@ init_oa_sys_vars(struct gen_perf_config *perf, const struct gen_device_info *dev
{ {
uint64_t min_freq_mhz = 0, max_freq_mhz = 0; uint64_t min_freq_mhz = 0, max_freq_mhz = 0;
if (likely(!(INTEL_DEBUG & DEBUG_NO_OACONFIG))) { if (!(INTEL_DEBUG & DEBUG_NO_OACONFIG)) {
if (!read_sysfs_drm_device_file_uint64(perf, "gt_min_freq_mhz", &min_freq_mhz)) if (!read_sysfs_drm_device_file_uint64(perf, "gt_min_freq_mhz", &min_freq_mhz))
return false; return false;
@@ -758,7 +758,7 @@ load_oa_metrics(struct gen_perf_config *perf, int fd,
*/ */
oa_register(perf); oa_register(perf);
if (likely(!(INTEL_DEBUG & DEBUG_NO_OACONFIG))) { if (!(INTEL_DEBUG & DEBUG_NO_OACONFIG)) {
if (kernel_has_dynamic_config_support(perf, fd)) if (kernel_has_dynamic_config_support(perf, fd))
init_oa_configs(perf, fd, devinfo); init_oa_configs(perf, fd, devinfo);
else else