iris: compctrl
oh, also run things
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@@ -506,7 +506,7 @@ submit_batch(struct iris_batch *batch, int in_fence_fd, int *out_fence_fd)
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execbuf.flags |= I915_EXEC_FENCE_OUT;
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}
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#if 0
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#if 1
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int ret = drm_ioctl(batch->screen->fd, cmd, &execbuf);
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if (ret != 0)
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ret = -errno;
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@@ -1310,12 +1310,29 @@ iris_create_vertex_elements(struct pipe_context *ctx,
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uint32_t *ve_pack_dest = &cso->vertex_elements[1];
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for (int i = 0; i < count; i++) {
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enum isl_format isl_format =
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iris_isl_format_for_pipe_format(state[i].src_format);
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unsigned comp[4] = { VFCOMP_STORE_SRC, VFCOMP_STORE_SRC,
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VFCOMP_STORE_SRC, VFCOMP_STORE_SRC };
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switch (isl_format_get_num_channels(isl_format)) {
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case 0: comp[0] = VFCOMP_STORE_0;
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case 1: comp[1] = VFCOMP_STORE_0;
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case 2: comp[2] = VFCOMP_STORE_0;
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case 3:
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comp[3] = isl_format_has_int_channel(isl_format) ? VFCOMP_STORE_1_INT
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: VFCOMP_STORE_1_FP;
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break;
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}
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iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) {
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ve.VertexBufferIndex = state[i].vertex_buffer_index;
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ve.Valid = true;
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ve.SourceElementOffset = state[i].src_offset;
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ve.SourceElementFormat =
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iris_isl_format_for_pipe_format(state[i].src_format);
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ve.SourceElementFormat = isl_format;
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ve.Component0Control = comp[0];
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ve.Component1Control = comp[1];
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ve.Component2Control = comp[2];
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ve.Component3Control = comp[3];
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}
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iris_pack_command(GENX(3DSTATE_VF_INSTANCING), cso->vf_instancing[i], vi) {
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