nir: Devendor load_sample_mask

AGX will use this too for its MSAA lowerings.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24148>

src/compiler/nir/nir_intrinsics.py

@@ -958,6 +958,14 @@ system_value("color1", 4)
 # System value for internal compute shaders in radeonsi.
 system_value("user_data_amd", 4)
 
+# In a fragment shader, the current sample mask. At the beginning of the shader,
+# this is the same as load_sample_mask_in, but as the shader is executed, it may
+# be affected by writes, discards, etc.
+#
+# No frontend generates this, but drivers may use it for internal lowerings.
+intrinsic("load_sample_mask", [], 1, [], flags=[CAN_ELIMINATE], sysval=True,
+          bit_sizes=[32])
+
 # Barycentric coordinate intrinsics.
 #
 # These set up the barycentric coordinates for a particular interpolation.
@@ -1327,10 +1335,6 @@ system_value("sample_positions_pan", 1, bit_sizes=[64])
 # In a fragment shader, is the framebuffer single-sampled? 0/~0 bool
 system_value("multisampled_pan", 1, bit_sizes=[32])
 
-# In a fragment shader, the current coverage mask. Affected by writes.
-intrinsic("load_coverage_mask_pan", [], 1, [], flags=[CAN_ELIMINATE],
-          sysval=True, bit_sizes=[32])
-
 # R600 specific instrincs
 #
 # location where the tesselation data is stored in LDS

src/panfrost/compiler/bifrost_compile.c

@@ -1672,7 +1672,7 @@ bi_emit_intrinsic(bi_builder *b, nir_intrinsic_instr *instr)
       bi_u16_to_u32_to(b, dst, bi_half(bi_preload(b, 61), false));
       break;
 
-   case nir_intrinsic_load_coverage_mask_pan:
+   case nir_intrinsic_load_sample_mask:
       bi_mov_i32_to(b, dst, bi_coverage(b));
       break;
 
@@ -4601,7 +4601,7 @@ bi_lower_sample_mask_writes(nir_builder *b, nir_instr *instr, void *data)
 
    b->cursor = nir_before_instr(&intr->instr);
 
-   nir_ssa_def *orig = nir_load_coverage_mask_pan(b);
+   nir_ssa_def *orig = nir_load_sample_mask(b);
 
    nir_instr_rewrite_src_ssa(
       instr, &intr->src[0],