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broadcom/compiler: add new SFU instructions in V3D 7.x

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Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27211>
This commit is contained in:
Iago Toral Quiroga
2024-01-16 09:28:17 +01:00
committed by Marge Bot
parent 7bdc8898b1
commit 9bbfbc2089
4 changed files with 62 additions and 0 deletions
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25
src/broadcom/compiler/v3d_compiler.h
View File

@@ -1313,6 +1313,23 @@ vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
a, c->undef)); \
}
#define VIR_SFU2(name) \
static inline struct qreg \
vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
{ \
return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
c->undef, \
a, b)); \
} \
static inline struct qinst * \
vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
struct qreg a, struct qreg b) \
{ \
return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
dest, \
a, b)); \
}
#define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
#define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
#define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
@@ -1412,6 +1429,14 @@ VIR_SFU(LOG)
VIR_SFU(SIN)
VIR_SFU(RSQRT2)
VIR_SFU(BALLOT)
VIR_SFU(BCASTF)
VIR_SFU(ALLEQ)
VIR_SFU(ALLFEQ)
VIR_SFU2(ROTQ)
VIR_SFU2(ROT)
VIR_SFU2(SHUFFLE)
VIR_A_ALU2(VPACK)
VIR_A_ALU2(V8PACK)
VIR_A_ALU2(V10PACK)

22
src/broadcom/qpu/qpu_instr.c
View File

@@ -183,6 +183,13 @@ v3d_qpu_add_op_name(enum v3d_qpu_add_op op)
[V3D_QPU_A_V8PACK] = "v8pack",
[V3D_QPU_A_V10PACK] = "v10pack",
[V3D_QPU_A_V11FPACK] = "v11fpack",
[V3D_QPU_A_BALLOT] = "ballot",
[V3D_QPU_A_BCASTF] = "bcastf",
[V3D_QPU_A_ALLEQ] = "alleq",
[V3D_QPU_A_ALLFEQ] = "allfeq",
[V3D_QPU_A_ROTQ] = "rotq",
[V3D_QPU_A_ROT] = "rot",
[V3D_QPU_A_SHUFFLE] = "shuffle",
};
if (op >= ARRAY_SIZE(op_names))
@@ -477,6 +484,14 @@ static const uint8_t add_op_args[] = {
[V3D_QPU_A_V8PACK] = D | A | B,
[V3D_QPU_A_V10PACK] = D | A | B,
[V3D_QPU_A_V11FPACK] = D | A | B,
[V3D_QPU_A_BALLOT] = D | A,
[V3D_QPU_A_BCASTF] = D | A,
[V3D_QPU_A_ALLEQ] = D | A,
[V3D_QPU_A_ALLFEQ] = D | A,
[V3D_QPU_A_ROTQ] = D | A | B,
[V3D_QPU_A_ROT] = D | A | B,
[V3D_QPU_A_SHUFFLE] = D | A | B,
};
static const uint8_t mul_op_args[] = {
@@ -740,6 +755,13 @@ v3d_qpu_instr_is_sfu(const struct v3d_qpu_instr *inst)
case V3D_QPU_A_LOG:
case V3D_QPU_A_SIN:
case V3D_QPU_A_RSQRT2:
case V3D_QPU_A_BALLOT:
case V3D_QPU_A_BCASTF:
case V3D_QPU_A_ALLEQ:
case V3D_QPU_A_ALLFEQ:
case V3D_QPU_A_ROTQ:
case V3D_QPU_A_ROT:
case V3D_QPU_A_SHUFFLE:
return true;
default:
return false;

7
src/broadcom/qpu/qpu_instr.h
View File

@@ -235,6 +235,13 @@ enum v3d_qpu_add_op {
V3D_QPU_A_V8PACK,
V3D_QPU_A_V10PACK,
V3D_QPU_A_V11FPACK,
V3D_QPU_A_BALLOT,
V3D_QPU_A_BCASTF,
V3D_QPU_A_ALLEQ,
V3D_QPU_A_ALLFEQ,
V3D_QPU_A_ROTQ,
V3D_QPU_A_ROT,
V3D_QPU_A_SHUFFLE,
};
enum v3d_qpu_mul_op {

8
src/broadcom/qpu/qpu_pack.c
View File

@@ -721,6 +721,10 @@ static const struct opcode_desc add_ops_v71[] = {
{ 188, 188, .raddr_mask = OP_MASK(35), V3D_QPU_A_LOG, 71 },
{ 188, 188, .raddr_mask = OP_MASK(36), V3D_QPU_A_SIN, 71 },
{ 188, 188, .raddr_mask = OP_MASK(37), V3D_QPU_A_RSQRT2, 71 },
{ 188, 188, .raddr_mask = OP_MASK(38), V3D_QPU_A_BALLOT, 71 },
{ 188, 188, .raddr_mask = OP_MASK(39), V3D_QPU_A_BCASTF, 71 },
{ 188, 188, .raddr_mask = OP_MASK(40), V3D_QPU_A_ALLEQ, 71 },
{ 188, 188, .raddr_mask = OP_MASK(41), V3D_QPU_A_ALLFEQ, 71 },
{ 189, 189, .raddr_mask = ANYOPMASK, V3D_QPU_A_LDVPMG_IN, 71 },
@@ -802,6 +806,10 @@ static const struct opcode_desc add_ops_v71[] = {
{ 250, 250, .raddr_mask = ANYOPMASK, V3D_QPU_A_V10PACK, 71 },
{ 251, 251, .raddr_mask = ANYOPMASK, V3D_QPU_A_V11FPACK, 71 },
{ 252, 252, .raddr_mask = ANYOPMASK, V3D_QPU_A_ROTQ, 71 },
{ 253, 253, .raddr_mask = ANYOPMASK, V3D_QPU_A_ROT, 71 },
{ 254, 254, .raddr_mask = ANYOPMASK, V3D_QPU_A_SHUFFLE, 71 },
};
static const struct opcode_desc mul_ops_v71[] = {