intel/compiler: drop glsl options from brw_compiler

Only the nir options are used now, since i965 was dropped,
the glsl options come from the state tracker

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14102>

src/gallium/drivers/crocus/crocus_program.c

@@ -1396,7 +1396,7 @@ crocus_compile_tcs(struct crocus_context *ice,
    struct crocus_screen *screen = (struct crocus_screen *)ice->ctx.screen;
    const struct brw_compiler *compiler = screen->compiler;
    const struct nir_shader_compiler_options *options =
-      compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].NirOptions;
+      compiler->nir_options[MESA_SHADER_TESS_CTRL];
    void *mem_ctx = ralloc_context(NULL);
    struct brw_tcs_prog_data *tcs_prog_data =
       rzalloc(mem_ctx, struct brw_tcs_prog_data);

src/gallium/drivers/crocus/crocus_screen.c

@@ -663,7 +663,7 @@ crocus_get_compiler_options(struct pipe_screen *pscreen,
    gl_shader_stage stage = stage_from_pipe(pstage);
    assert(ir == PIPE_SHADER_IR_NIR);
 
-   return screen->compiler->glsl_compiler_options[stage].NirOptions;
+   return screen->compiler->nir_options[stage];
 }
 
 static struct disk_cache *

src/gallium/drivers/iris/iris_program.c

@@ -1486,7 +1486,7 @@ iris_compile_tcs(struct iris_screen *screen,
 {
    const struct brw_compiler *compiler = screen->compiler;
    const struct nir_shader_compiler_options *options =
-      compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].NirOptions;
+      compiler->nir_options[MESA_SHADER_TESS_CTRL];
    void *mem_ctx = ralloc_context(NULL);
    struct brw_tcs_prog_data *tcs_prog_data =
       rzalloc(mem_ctx, struct brw_tcs_prog_data);
@@ -2471,7 +2471,7 @@ iris_create_compute_state(struct pipe_context *ctx,
    struct iris_screen *screen = (void *) ctx->screen;
    struct u_upload_mgr *uploader = ice->shaders.uploader_unsync;
    const nir_shader_compiler_options *options =
-      screen->compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions;
+      screen->compiler->nir_options[MESA_SHADER_COMPUTE];
 
    nir_shader *nir;
    switch (state->ir_type) {

src/gallium/drivers/iris/iris_screen.c

@@ -650,7 +650,7 @@ iris_get_compiler_options(struct pipe_screen *pscreen,
    gl_shader_stage stage = stage_from_pipe(pstage);
    assert(ir == PIPE_SHADER_IR_NIR);
 
-   return screen->compiler->glsl_compiler_options[stage].NirOptions;
+   return screen->compiler->nir_options[stage];
 }
 
 static struct disk_cache *

src/intel/blorp/blorp.c

@@ -219,8 +219,7 @@ blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
 {
    const struct brw_compiler *compiler = blorp->compiler;
 
-   nir->options =
+   nir->options = compiler->nir_options[MESA_SHADER_FRAGMENT];
-      compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
 
    memset(wm_prog_data, 0, sizeof(*wm_prog_data));
 
@@ -265,8 +264,7 @@ blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
 {
    const struct brw_compiler *compiler = blorp->compiler;
 
-   nir->options =
+   nir->options = compiler->nir_options[MESA_SHADER_VERTEX];
-      compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
 
    brw_preprocess_nir(compiler, nir, NULL);
    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
@@ -301,8 +299,7 @@ blorp_compile_cs(struct blorp_context *blorp, void *mem_ctx,
 {
    const struct brw_compiler *compiler = blorp->compiler;
 
-   nir->options =
+   nir->options = compiler->nir_options[MESA_SHADER_COMPUTE];
-      compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions;
 
    memset(cs_prog_data, 0, sizeof(*cs_prog_data));
 

src/intel/compiler/brw_compiler.c

@@ -156,21 +156,9 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
 
    /* We want the GLSL compiler to emit code that uses condition codes */
    for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
-      compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
-      compiler->glsl_compiler_options[i].MaxIfDepth =
-         devinfo->ver < 6 ? 16 : UINT_MAX;
-
-      /* We handle this in NIR */
-      compiler->glsl_compiler_options[i].EmitNoIndirectInput = false;
-      compiler->glsl_compiler_options[i].EmitNoIndirectOutput = false;
-      compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
-      compiler->glsl_compiler_options[i].EmitNoIndirectTemp = false;
-
-      bool is_scalar = compiler->scalar_stage[i];
-      compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
-
       struct nir_shader_compiler_options *nir_options =
          rzalloc(compiler, struct nir_shader_compiler_options);
+      bool is_scalar = compiler->scalar_stage[i];
       if (is_scalar) {
          *nir_options = scalar_nir_options;
       } else {
@@ -201,9 +189,7 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
       nir_options->force_indirect_unrolling |=
          brw_nir_no_indirect_mask(compiler, i);
 
-      compiler->glsl_compiler_options[i].NirOptions = nir_options;
+      compiler->nir_options[i] = nir_options;
-
-      compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
    }
 
    return compiler;

src/intel/compiler/brw_compiler.h

@@ -38,6 +38,7 @@ struct ra_regs;
 struct nir_shader;
 struct brw_program;
 
+struct nir_shader_compiler_options;
 typedef struct nir_shader nir_shader;
 
 struct brw_compiler {
@@ -74,7 +75,7 @@ struct brw_compiler {
 
    bool scalar_stage[MESA_ALL_SHADER_STAGES];
    bool use_tcs_8_patch;
-   struct gl_shader_compiler_options glsl_compiler_options[MESA_ALL_SHADER_STAGES];
+   struct nir_shader_compiler_options *nir_options[MESA_ALL_SHADER_STAGES];
 
    /**
     * Apply workarounds for SIN and COS output range problems.

src/intel/compiler/brw_nir_lower_shader_calls.c

@@ -254,7 +254,7 @@ brw_nir_create_trivial_return_shader(const struct brw_compiler *compiler,
                                      void *mem_ctx)
 {
    const nir_shader_compiler_options *nir_options =
-      compiler->glsl_compiler_options[MESA_SHADER_CALLABLE].NirOptions;
+      compiler->nir_options[MESA_SHADER_CALLABLE];
 
    nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_CALLABLE,
                                                   nir_options,

src/intel/compiler/brw_nir_rt.c

@@ -417,7 +417,7 @@ brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler,
 {
    const struct intel_device_info *devinfo = compiler->devinfo;
    const nir_shader_compiler_options *nir_options =
-      compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions;
+      compiler->nir_options[MESA_SHADER_COMPUTE];
 
    STATIC_ASSERT(sizeof(struct brw_rt_raygen_trampoline_params) == 32);
 

src/intel/vulkan/anv_pipeline.c

@@ -93,7 +93,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
    const struct anv_physical_device *pdevice = device->physical;
    const struct brw_compiler *compiler = pdevice->compiler;
    const nir_shader_compiler_options *nir_options =
-      compiler->glsl_compiler_options[stage].NirOptions;
+      compiler->nir_options[stage];
 
    uint32_t *spirv = (uint32_t *) module->data;
    assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
@@ -749,7 +749,7 @@ anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline,
    const struct brw_compiler *compiler =
       pipeline->device->physical->compiler;
    const nir_shader_compiler_options *nir_options =
-      compiler->glsl_compiler_options[stage->stage].NirOptions;
+      compiler->nir_options[stage->stage];
    nir_shader *nir;
 
    nir = anv_device_search_for_nir(pipeline->device, cache,
@@ -1691,7 +1691,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
 
       anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
 
-      if (prev_stage && compiler->glsl_compiler_options[s].NirOptions->unify_interfaces) {
+      if (prev_stage && compiler->nir_options[s]->unify_interfaces) {
          prev_stage->nir->info.outputs_written |= stages[s].nir->info.inputs_read &
                   ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
          stages[s].nir->info.inputs_read |= prev_stage->nir->info.outputs_written &