OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: rename radv_shader_variant to radv_shader

Browse Source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13548>
This commit is contained in:
Samuel Pitoiset
2021-10-27 13:20:29 +02:00
committed by Marge Bot
parent eeb034f2cc
commit 9b80f4d5f2
9 changed files with 226 additions and 230 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/amd/vulkan/layers/radv_sqtt_layer.c
View File

@@ -821,7 +821,7 @@ sqtt_DebugMarkerSetObjectTagEXT(VkDevice device, const VkDebugMarkerObjectTagInf
static enum rgp_hardware_stages
radv_mesa_to_rgp_shader_stage(struct radv_pipeline *pipeline, gl_shader_stage stage)
{
struct radv_shader_variant *shader = pipeline->shaders[stage];
struct radv_shader *shader = pipeline->shaders[stage];
switch (stage) {
case MESA_SHADER_VERTEX:
@@ -870,7 +870,7 @@ radv_add_code_object(struct radv_device *device, struct radv_pipeline *pipeline)
record->pipeline_hash[1] = pipeline->pipeline_hash;
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
struct radv_shader_variant *shader = pipeline->shaders[i];
struct radv_shader *shader = pipeline->shaders[i];
uint8_t *code;
uint64_t va;
@@ -884,7 +884,7 @@ radv_add_code_object(struct radv_device *device, struct radv_pipeline *pipeline)
}
memcpy(code, shader->code_ptr, shader->code_size);
va = radv_shader_variant_get_va(shader);
va = radv_shader_get_va(shader);
record->shader_data[i].hash[0] = (uint64_t)(uintptr_t)shader;
record->shader_data[i].hash[1] = (uint64_t)(uintptr_t)shader >> 32;
@@ -923,13 +923,13 @@ radv_register_pipeline(struct radv_device *device, struct radv_pipeline *pipelin
/* Find the lowest shader BO VA. */
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
struct radv_shader_variant *shader = pipeline->shaders[i];
struct radv_shader *shader = pipeline->shaders[i];
uint64_t va;
if (!shader)
continue;
va = radv_shader_variant_get_va(shader);
va = radv_shader_get_va(shader);
base_va = MIN2(base_va, va);
}

26
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -767,7 +767,7 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bi
struct radv_userdata_info *
radv_lookup_user_sgpr(struct radv_pipeline *pipeline, gl_shader_stage stage, int idx)
{
struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
struct radv_shader *shader = radv_get_shader(pipeline, stage);
return &shader->info.user_sgprs_locs.shader_data[idx];
}
@@ -1056,14 +1056,14 @@ radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeli
}
static void
radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_variant *shader)
radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader)
{
uint64_t va;
if (!shader)
return;
va = radv_shader_variant_get_va(shader);
va = radv_shader_get_va(shader);
si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
}
@@ -1357,7 +1357,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
* Culling is currently disabled, so re-emit RSRC2 to reduce LDS usage.
* API GS always needs LDS, so this isn't useful there.
*/
struct radv_shader_variant *v = pipeline->shaders[pipeline->graphics.last_vgt_api_stage];
struct radv_shader *v = pipeline->shaders[pipeline->graphics.last_vgt_api_stage];
radeon_set_sh_reg(cmd_buffer->cs, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
(v->config.rsrc2 & C_00B22C_LDS_SIZE) |
S_00B22C_LDS_SIZE(v->info.num_lds_blocks_when_not_culling));
@@ -2723,7 +2723,7 @@ radv_cmp_vs_prolog(const void *a_, const void *b_)
}
static struct radv_shader_prolog *
lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_variant *vs_shader,
lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shader,
uint32_t *nontrivial_divisors)
{
STATIC_ASSERT(sizeof(union vs_prolog_key_header) == 4);
@@ -2855,7 +2855,7 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_variant
}
static void
emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_variant *vs_shader,
emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shader,
struct radv_shader_prolog *prolog, bool pipeline_is_dirty)
{
/* no need to re-emit anything in this case */
@@ -2907,7 +2907,7 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_variant
}
static void
emit_prolog_inputs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_variant *vs_shader,
emit_prolog_inputs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shader,
uint32_t nontrivial_divisors, bool pipeline_is_dirty)
{
/* no need to re-emit anything in this case */
@@ -2916,7 +2916,7 @@ emit_prolog_inputs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_varian
return;
struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;
uint64_t input_va = radv_shader_variant_get_va(vs_shader);
uint64_t input_va = radv_shader_get_va(vs_shader);
if (nontrivial_divisors) {
unsigned inputs_offset;
@@ -2960,7 +2960,7 @@ static void
radv_emit_vertex_state(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
{
struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
struct radv_shader_variant *vs_shader = radv_get_shader(pipeline, MESA_SHADER_VERTEX);
struct radv_shader *vs_shader = radv_get_shader(pipeline, MESA_SHADER_VERTEX);
if (!vs_shader->info.vs.has_prolog)
return;
@@ -3181,7 +3181,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag
{
struct radv_descriptor_state *descriptors_state =
radv_get_descriptors_state(cmd_buffer, bind_point);
struct radv_shader_variant *shader, *prev_shader;
struct radv_shader *shader, *prev_shader;
bool need_push_constants = false;
unsigned offset;
void *ptr;
@@ -3296,7 +3296,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_
if ((pipeline_is_dirty || (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
cmd_buffer->state.pipeline->vb_desc_usage_mask) {
struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
struct radv_shader_variant *vs_shader = radv_get_shader(pipeline, MESA_SHADER_VERTEX);
struct radv_shader *vs_shader = radv_get_shader(pipeline, MESA_SHADER_VERTEX);
enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class;
unsigned vb_offset;
void *vb_ptr;
@@ -6432,7 +6432,7 @@ radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer, const struct rad
/* Remember small draw state. */
cmd_buffer->state.last_nggc_skip = skip;
const struct radv_shader_variant *v = pipeline->shaders[stage];
const struct radv_shader *v = pipeline->shaders[stage];
assert(v->info.has_ngg_culling == nggc_supported);
/* Find the user SGPR. */
@@ -6879,7 +6879,7 @@ static void
radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline,
const struct radv_dispatch_info *info)
{
struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
struct radv_shader *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
struct radeon_winsys *ws = cmd_buffer->device->ws;
bool predicating = cmd_buffer->state.predicating;

16
src/amd/vulkan/radv_debug.c
View File

@@ -297,7 +297,7 @@ si_add_split_disasm(const char *disasm, uint64_t start_addr, unsigned *num,
}
static void
radv_dump_annotated_shader(struct radv_shader_variant *shader, gl_shader_stage stage,
radv_dump_annotated_shader(struct radv_shader *shader, gl_shader_stage stage,
struct ac_wave_info *waves, unsigned num_waves, FILE *f)
{
uint64_t start_addr, end_addr;
@@ -306,7 +306,7 @@ radv_dump_annotated_shader(struct radv_shader_variant *shader, gl_shader_stage s
if (!shader)
return;
start_addr = radv_shader_variant_get_va(shader);
start_addr = radv_shader_get_va(shader);
end_addr = start_addr + shader->code_size;
/* See if any wave executes the shader. */
@@ -403,7 +403,7 @@ radv_dump_annotated_shaders(struct radv_pipeline *pipeline, VkShaderStageFlagBit
}
static void
radv_dump_spirv(struct radv_shader_variant *shader, const char *sha1, const char *dump_dir)
radv_dump_spirv(struct radv_shader *shader, const char *sha1, const char *dump_dir)
{
char dump_path[512];
FILE *f;
@@ -418,7 +418,7 @@ radv_dump_spirv(struct radv_shader_variant *shader, const char *sha1, const char
}
static void
radv_dump_shader(struct radv_pipeline *pipeline, struct radv_shader_variant *shader,
radv_dump_shader(struct radv_pipeline *pipeline, struct radv_shader *shader,
gl_shader_stage stage, const char *dump_dir, FILE *f)
{
if (!shader)
@@ -874,7 +874,7 @@ radv_trap_handler_finish(struct radv_device *device)
if (unlikely(device->trap_handler_shader)) {
ws->buffer_make_resident(ws, device->trap_handler_shader->bo, false);
radv_shader_variant_destroy(device, device->trap_handler_shader);
radv_shader_destroy(device, device->trap_handler_shader);
}
if (unlikely(device->tma_bo)) {
@@ -886,15 +886,15 @@ radv_trap_handler_finish(struct radv_device *device)
static void
radv_dump_faulty_shader(struct radv_device *device, uint64_t faulty_pc)
{
struct radv_shader_variant *shader;
struct radv_shader *shader;
uint64_t start_addr, end_addr;
uint32_t instr_offset;
shader = radv_find_shader_variant(device, faulty_pc);
shader = radv_find_shader(device, faulty_pc);
if (!shader)
return;
start_addr = radv_shader_variant_get_va(shader);
start_addr = radv_shader_get_va(shader);
end_addr = start_addr + shader->code_size;
instr_offset = faulty_pc - start_addr;

120
src/amd/vulkan/radv_pipeline.c
View File

@@ -147,10 +147,9 @@ radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
if (pipeline->graphics.last_vgt_api_stage == MESA_SHADER_NONE)
return false;
struct radv_shader_variant *variant =
pipeline->shaders[pipeline->graphics.last_vgt_api_stage];
struct radv_shader *shader = pipeline->shaders[pipeline->graphics.last_vgt_api_stage];
return variant->info.is_ngg;
return shader->info.is_ngg;
}
bool
@@ -161,10 +160,9 @@ radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
assert(radv_pipeline_has_ngg(pipeline));
struct radv_shader_variant *variant =
pipeline->shaders[pipeline->graphics.last_vgt_api_stage];
struct radv_shader *shader = pipeline->shaders[pipeline->graphics.last_vgt_api_stage];
return variant->info.is_ngg_passthrough;
return shader->info.is_ngg_passthrough;
}
bool
@@ -187,10 +185,10 @@ radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
if (pipeline->shaders[i])
radv_shader_variant_destroy(device, pipeline->shaders[i]);
radv_shader_destroy(device, pipeline->shaders[i]);
if (pipeline->gs_copy_shader)
radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
radv_shader_destroy(device, pipeline->gs_copy_shader);
if (pipeline->cs.buf)
free(pipeline->cs.buf);
@@ -943,7 +941,7 @@ radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
pass->attachments + subpass->depth_stencil_attachment->attachment;
bool has_stencil = vk_format_has_stencil(attachment->format);
struct radv_dsa_order_invariance order_invariance[2];
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
/* Compute depth/stencil order invariance in order to know if
* it's safe to enable out-of-order.
@@ -1158,7 +1156,7 @@ gfx103_pipeline_init_vrs_state(struct radv_pipeline *pipeline,
{
const VkPipelineMultisampleStateCreateInfo *vkms =
radv_pipeline_get_multisample_state(pCreateInfo);
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_multisample_state *ms = &pipeline->graphics.ms;
struct radv_vrs_state *vrs = &pipeline->graphics.vrs;
@@ -1474,8 +1472,8 @@ radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline,
const struct radv_graphics_pipeline_create_info *extra)
{
const VkPipelineInputAssemblyStateCreateInfo *ia_state = pCreateInfo->pInputAssemblyState;
struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
struct radv_shader *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
struct radv_shader *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology);
@@ -2250,7 +2248,7 @@ radv_pipeline_init_gs_ring_state(struct radv_pipeline *pipeline, const struct gf
pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
}
struct radv_shader_variant *
struct radv_shader *
radv_get_shader(const struct radv_pipeline *pipeline, gl_shader_stage stage)
{
if (stage == MESA_SHADER_VERTEX) {
@@ -3410,9 +3408,9 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
bool found_in_application_cache = true;
if (!keep_executable_info &&
radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
stack_sizes, num_stack_sizes,
&found_in_application_cache)) {
radv_create_shaders_from_pipeline_cache(device, cache, hash, pipeline->shaders,
stack_sizes, num_stack_sizes,
&found_in_application_cache)) {
if (modules[MESA_SHADER_GEOMETRY] && !pipeline->shaders[MESA_SHADER_GEOMETRY]->info.is_ngg) {
/* We use the CS slot because graphics pipelines might use all the other ones. */
pipeline->gs_copy_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
@@ -3632,7 +3630,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
pipeline->shaders[MESA_SHADER_FRAGMENT] = radv_shader_variant_compile(
pipeline->shaders[MESA_SHADER_FRAGMENT] = radv_shader_compile(
device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1, pipeline_layout,
pipeline_key, infos + MESA_SHADER_FRAGMENT, keep_executable_info,
keep_statistic_info, &binaries[MESA_SHADER_FRAGMENT]);
@@ -3647,7 +3645,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(
pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_compile(
device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2, pipeline_layout, pipeline_key,
&infos[MESA_SHADER_TESS_CTRL], keep_executable_info, keep_statistic_info,
&binaries[MESA_SHADER_TESS_CTRL]);
@@ -3665,7 +3663,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(
pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_compile(
device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2, pipeline_layout, pipeline_key,
&infos[MESA_SHADER_GEOMETRY], keep_executable_info,
keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
@@ -3679,7 +3677,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
if (modules[i] && !pipeline->shaders[i]) {
radv_start_feedback(stage_feedbacks[i]);
pipeline->shaders[i] = radv_shader_variant_compile(
pipeline->shaders[i] = radv_shader_compile(
device, modules[i], &nir[i], 1, pipeline_layout, pipeline_key, infos + i,
keep_executable_info, keep_statistic_info, &binaries[i]);
@@ -4265,7 +4263,7 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
radv_pipeline_get_depth_stencil_state(pCreateInfo);
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_render_pass_attachment *attachment = NULL;
uint32_t db_render_control = 0, db_render_override2 = 0;
uint32_t db_render_override = 0;
@@ -4402,9 +4400,9 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
const struct radv_pipeline *pipeline)
{
const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
const struct radv_shader_variant *vs = pipeline->shaders[MESA_SHADER_TESS_EVAL]
? pipeline->shaders[MESA_SHADER_TESS_EVAL]
: pipeline->shaders[MESA_SHADER_VERTEX];
const struct radv_shader *vs = pipeline->shaders[MESA_SHADER_TESS_EVAL]
? pipeline->shaders[MESA_SHADER_TESS_EVAL]
: pipeline->shaders[MESA_SHADER_VERTEX];
unsigned vgt_primitiveid_en = 0;
uint32_t vgt_gs_mode = 0;
@@ -4412,7 +4410,7 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
return;
if (radv_pipeline_has_gs(pipeline)) {
const struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
const struct radv_shader *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
pipeline->device->physical_device->rad_info.chip_class);
@@ -4428,9 +4426,9 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
static void
radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
const struct radv_shader *shader)
{
uint64_t va = radv_shader_variant_get_va(shader);
uint64_t va = radv_shader_get_va(shader);
radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
radeon_emit(cs, va >> 8);
@@ -4501,9 +4499,9 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
static void
radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
const struct radv_shader *shader)
{
uint64_t va = radv_shader_variant_get_va(shader);
uint64_t va = radv_shader_get_va(shader);
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
radeon_emit(cs, va >> 8);
@@ -4514,10 +4512,10 @@ radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs, const struct radv_pipelin
static void
radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
const struct radv_shader *shader)
{
unsigned num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
uint64_t va = radv_shader_variant_get_va(shader);
uint64_t va = radv_shader_get_va(shader);
uint32_t rsrc2 = shader->config.rsrc2;
radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
@@ -4535,12 +4533,12 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, const struct radv_pipelin
static void
radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
const struct radv_shader *shader)
{
uint64_t va = radv_shader_variant_get_va(shader);
uint64_t va = radv_shader_get_va(shader);
gl_shader_stage es_type =
radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
struct radv_shader_variant *es = es_type == MESA_SHADER_TESS_EVAL
struct radv_shader *es = es_type == MESA_SHADER_TESS_EVAL
? pipeline->shaders[MESA_SHADER_TESS_EVAL]
: pipeline->shaders[MESA_SHADER_VERTEX];
const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
@@ -4567,7 +4565,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
unsigned nparams;
if (es_type == MESA_SHADER_TESS_EVAL) {
struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
struct radv_shader *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
break_wave_at_eoi = true;
@@ -4609,7 +4607,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
ngg_state->vgt_esgs_ring_itemsize);
/* NGG specific registers. */
struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
struct radv_shader *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
radeon_set_context_reg(
@@ -4675,9 +4673,9 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
static void
radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
const struct radv_shader *shader)
{
uint64_t va = radv_shader_variant_get_va(shader);
uint64_t va = radv_shader_get_va(shader);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
@@ -4702,7 +4700,7 @@ static void
radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *vs;
struct radv_shader *vs;
/* Skip shaders merged into HS/GS */
vs = pipeline->shaders[MESA_SHADER_VERTEX];
@@ -4723,7 +4721,7 @@ static void
radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *tes, *tcs;
struct radv_shader *tes, *tcs;
tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
@@ -4752,7 +4750,7 @@ radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
const struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
struct radv_shader *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches;
unsigned ls_hs_config;
@@ -4833,7 +4831,7 @@ radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
static void
radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline,
const struct radv_shader_variant *gs)
const struct radv_shader *gs)
{
const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
unsigned gs_max_out_vertices;
@@ -4874,7 +4872,7 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
gs_state->vgt_esgs_ring_itemsize);
va = radv_shader_variant_get_va(gs);
va = radv_shader_get_va(gs);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
@@ -4917,7 +4915,7 @@ static void
radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *gs;
struct radv_shader *gs;
gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
if (!gs)
@@ -4960,7 +4958,7 @@ offset_to_ps_input(uint32_t offset, bool flat_shade, bool explicit, bool float16
static void
radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs, const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
uint32_t ps_input_cntl[32];
@@ -5048,7 +5046,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs, const struct radv
static uint32_t
radv_compute_db_shader_control(const struct radv_device *device,
const struct radv_pipeline *pipeline,
const struct radv_shader_variant *ps)
const struct radv_shader *ps)
{
unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
unsigned z_order;
@@ -5087,12 +5085,12 @@ static void
radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps;
struct radv_shader *ps;
uint64_t va;
assert(pipeline->shaders[MESA_SHADER_FRAGMENT]);
ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
va = radv_shader_variant_get_va(ps);
va = radv_shader_get_va(ps);
radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
radeon_emit(cs, va >> 8);
@@ -5300,7 +5298,7 @@ radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs,
static bool
gfx103_pipeline_vrs_coarse_shading(const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_device *device = pipeline->device;
if (device->instance->debug_flags & RADV_DEBUG_NO_VRS_FLAT_SHADING)
@@ -5343,7 +5341,7 @@ gfx103_pipeline_generate_vrs_state(struct radeon_cmdbuf *ctx_cs,
* because discard at 2x2 pixel granularity degrades quality
* too much. MIN allows sample shading but not coarse shading.
*/
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
mode = ps->info.ps.can_discard ? V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU;
}
@@ -5439,7 +5437,7 @@ radv_pipeline_init_vertex_input_state(struct radv_pipeline *pipeline,
else
pipeline->next_vertex_stage = MESA_SHADER_GEOMETRY;
if (pipeline->next_vertex_stage == MESA_SHADER_VERTEX) {
const struct radv_shader_variant *vs_shader = pipeline->shaders[MESA_SHADER_VERTEX];
const struct radv_shader *vs_shader = pipeline->shaders[MESA_SHADER_VERTEX];
pipeline->can_use_simple_input = vs_shader->info.is_ngg == pipeline->device->physical_device->use_ngg &&
vs_shader->info.wave_size == pipeline->device->physical_device->ge_wave_size;
} else {
@@ -5452,13 +5450,13 @@ radv_pipeline_init_vertex_input_state(struct radv_pipeline *pipeline,
pipeline->vb_desc_alloc_size = util_bitcount(pipeline->vb_desc_usage_mask) * 16;
}
static struct radv_shader_variant *
static struct radv_shader *
radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
{
int i;
for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
struct radv_shader_variant *shader = radv_get_shader(pipeline, i);
struct radv_shader *shader = radv_get_shader(pipeline, i);
if (shader && shader->info.so.num_outputs > 0)
return shader;
@@ -5568,7 +5566,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
* color and Z formats to SPI_SHADER_ZERO. The hw will skip export
* instructions if any are present.
*/
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
ps->info.ps.can_discard) &&
!blend.spi_shader_col_format) {
@@ -5590,7 +5588,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
pipeline->graphics.cb_target_mask = blend.cb_target_mask;
if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
struct radv_shader *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
radv_pipeline_init_gs_ring_state(pipeline, &gs->info.gs_ring_info);
}
@@ -5681,8 +5679,8 @@ radv_CreateGraphicsPipelines(VkDevice _device, VkPipelineCache pipelineCache, ui
static void
radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
uint64_t va = radv_shader_variant_get_va(shader);
struct radv_shader *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
uint64_t va = radv_shader_get_va(shader);
struct radv_device *device = pipeline->device;
radeon_set_sh_reg(cs, R_00B830_COMPUTE_PGM_LO, va >> 8);
@@ -5698,7 +5696,7 @@ radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs, const struct radv_pipelin
static void
radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
struct radv_shader *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
struct radv_device *device = pipeline->device;
unsigned threads_per_threadgroup;
unsigned threadgroups_per_cu = 1;
@@ -5877,7 +5875,7 @@ radv_get_executable_count(const struct radv_pipeline *pipeline)
return ret;
}
static struct radv_shader_variant *
static struct radv_shader *
radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index,
gl_shader_stage *stage)
{
@@ -6012,7 +6010,7 @@ radv_GetPipelineExecutableStatisticsKHR(VkDevice _device,
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
gl_shader_stage stage;
struct radv_shader_variant *shader =
struct radv_shader *shader =
radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
@@ -6138,7 +6136,7 @@ radv_GetPipelineExecutableInternalRepresentationsKHR(
{
RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
gl_shader_stage stage;
struct radv_shader_variant *shader =
struct radv_shader *shader =
radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;

50
src/amd/vulkan/radv_pipeline_cache.c
View File

@@ -38,7 +38,7 @@ struct cache_entry {
};
uint32_t binary_sizes[MESA_SHADER_STAGES];
uint32_t num_stack_sizes;
struct radv_shader_variant *variants[MESA_SHADER_STAGES];
struct radv_shader *shaders[MESA_SHADER_STAGES];
char code[0];
};
@@ -91,8 +91,8 @@ radv_pipeline_cache_finish(struct radv_pipeline_cache *cache)
for (unsigned i = 0; i < cache->table_size; ++i)
if (cache->hash_table[i]) {
for (int j = 0; j < MESA_SHADER_STAGES; ++j) {
if (cache->hash_table[i]->variants[j])
radv_shader_variant_destroy(cache->device, cache->hash_table[i]->variants[j]);
if (cache->hash_table[i]->shaders[j])
radv_shader_destroy(cache->device, cache->hash_table[i]->shaders[j]);
}
vk_free(&cache->alloc, cache->hash_table[i]);
}
@@ -291,9 +291,9 @@ radv_is_cache_disabled(struct radv_device *device)
}
bool
radv_create_shader_variants_from_pipeline_cache(
radv_create_shaders_from_pipeline_cache(
struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1,
struct radv_shader_variant **variants, struct radv_pipeline_shader_stack_size **stack_sizes,
struct radv_shader **shaders, struct radv_pipeline_shader_stack_size **stack_sizes,
uint32_t *num_stack_sizes, bool *found_in_application_cache)
{
struct cache_entry *entry;
@@ -348,19 +348,19 @@ radv_create_shader_variants_from_pipeline_cache(
char *p = entry->code;
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (!entry->variants[i] && entry->binary_sizes[i]) {
if (!entry->shaders[i] && entry->binary_sizes[i]) {
struct radv_shader_binary *binary = calloc(1, entry->binary_sizes[i]);
memcpy(binary, p, entry->binary_sizes[i]);
p += entry->binary_sizes[i];
entry->variants[i] = radv_shader_variant_create(device, binary, false, true);
entry->shaders[i] = radv_shader_create(device, binary, false, true);
free(binary);
} else if (entry->binary_sizes[i]) {
p += entry->binary_sizes[i];
}
}
memcpy(variants, entry->variants, sizeof(entry->variants));
memcpy(shaders, entry->shaders, sizeof(entry->shaders));
if (num_stack_sizes) {
*num_stack_sizes = entry->num_stack_sizes;
@@ -374,8 +374,8 @@ radv_create_shader_variants_from_pipeline_cache(
vk_free(&cache->alloc, entry);
else {
for (int i = 0; i < MESA_SHADER_STAGES; ++i)
if (entry->variants[i])
p_atomic_inc(&entry->variants[i]->ref_count);
if (entry->shaders[i])
p_atomic_inc(&entry->shaders[i]->ref_count);
}
radv_pipeline_cache_unlock(cache);
@@ -384,7 +384,7 @@ radv_create_shader_variants_from_pipeline_cache(
void
radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipeline_cache *cache,
const unsigned char *sha1, struct radv_shader_variant **variants,
const unsigned char *sha1, struct radv_shader **shaders,
struct radv_shader_binary *const *binaries,
const struct radv_pipeline_shader_stack_size *stack_sizes,
uint32_t num_stack_sizes)
@@ -396,14 +396,14 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipel
struct cache_entry *entry = radv_pipeline_cache_search_unlocked(cache, sha1);
if (entry) {
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (entry->variants[i]) {
radv_shader_variant_destroy(cache->device, variants[i]);
variants[i] = entry->variants[i];
if (entry->shaders[i]) {
radv_shader_destroy(cache->device, shaders[i]);
shaders[i] = entry->shaders[i];
} else {
entry->variants[i] = variants[i];
entry->shaders[i] = shaders[i];
}
if (variants[i])
p_atomic_inc(&variants[i]->ref_count);
if (shaders[i])
p_atomic_inc(&shaders[i]->ref_count);
}
radv_pipeline_cache_unlock(cache);
return;
@@ -419,7 +419,7 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipel
size_t size = sizeof(*entry) + sizeof(*stack_sizes) * num_stack_sizes;
for (int i = 0; i < MESA_SHADER_STAGES; ++i)
if (variants[i])
if (shaders[i])
size += binaries[i]->total_size;
const size_t size_without_align = size;
size = align(size_without_align, alignof(struct cache_entry));
@@ -436,7 +436,7 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipel
char *p = entry->code;
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (!variants[i])
if (!shaders[i])
continue;
entry->binary_sizes[i] = binaries[i]->total_size;
@@ -476,15 +476,15 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipel
return;
}
/* We delay setting the variant so we have reproducible disk cache
/* We delay setting the shader so we have reproducible disk cache
* items.
*/
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (!variants[i])
if (!shaders[i])
continue;
entry->variants[i] = variants[i];
p_atomic_inc(&variants[i]->ref_count);
entry->shaders[i] = shaders[i];
p_atomic_inc(&shaders[i]->ref_count);
}
radv_pipeline_cache_add_entry(cache, entry);
@@ -528,7 +528,7 @@ radv_pipeline_cache_load(struct radv_pipeline_cache *cache, const void *data, si
if (dest_entry) {
memcpy(dest_entry, entry, size_of_entry);
for (int i = 0; i < MESA_SHADER_STAGES; ++i)
dest_entry->variants[i] = NULL;
dest_entry->shaders[i] = NULL;
radv_pipeline_cache_add_entry(cache, dest_entry);
}
p += size_of_entry;
@@ -625,7 +625,7 @@ radv_GetPipelineCacheData(VkDevice _device, VkPipelineCache _cache, size_t *pDat
memcpy(p, entry, size_of_entry);
for (int j = 0; j < MESA_SHADER_STAGES; ++j)
((struct cache_entry *)p)->variants[j] = NULL;
((struct cache_entry *)p)->shaders[j] = NULL;
p = (char *)p + size_of_entry;
}
*pDataSize = (char *)p - (char *)pData;

19
src/amd/vulkan/radv_private.h
View File

@@ -343,21 +343,21 @@ struct radv_pipeline_cache {
};
struct radv_shader_binary;
struct radv_shader_variant;
struct radv_shader;
struct radv_pipeline_shader_stack_size;
void radv_pipeline_cache_init(struct radv_pipeline_cache *cache, struct radv_device *device);
void radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
bool radv_pipeline_cache_load(struct radv_pipeline_cache *cache, const void *data, size_t size);
bool radv_create_shader_variants_from_pipeline_cache(
bool radv_create_shaders_from_pipeline_cache(
struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1,
struct radv_shader_variant **variants, struct radv_pipeline_shader_stack_size **stack_sizes,
struct radv_shader **shaders, struct radv_pipeline_shader_stack_size **stack_sizes,
uint32_t *num_stack_sizes, bool *found_in_application_cache);
void radv_pipeline_cache_insert_shaders(
struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1,
struct radv_shader_variant **variants, struct radv_shader_binary *const *binaries,
struct radv_shader **shaders, struct radv_shader_binary *const *binaries,
const struct radv_pipeline_shader_stack_size *stack_sizes, uint32_t num_stack_sizes);
enum radv_blit_ds_layout {
@@ -811,7 +811,7 @@ struct radv_device {
struct ac_thread_trace_data thread_trace;
/* Trap handler. */
struct radv_shader_variant *trap_handler_shader;
struct radv_shader *trap_handler_shader;
struct radeon_winsys_bo *tma_bo; /* Trap Memory Address */
uint32_t *tma_ptr;
@@ -1768,8 +1768,8 @@ struct radv_pipeline {
struct radv_dynamic_state dynamic_state;
bool need_indirect_descriptor_sets;
struct radv_shader_variant *shaders[MESA_SHADER_STAGES];
struct radv_shader_variant *gs_copy_shader;
struct radv_shader *shaders[MESA_SHADER_STAGES];
struct radv_shader *gs_copy_shader;
VkShaderStageFlags active_stages;
struct radeon_cmdbuf cs;
@@ -1843,7 +1843,7 @@ struct radv_pipeline {
unsigned scratch_bytes_per_wave;
/* Not NULL if graphics pipeline uses streamout. */
struct radv_shader_variant *streamout_shader;
struct radv_shader *streamout_shader;
/* Unique pipeline hash identifier. */
uint64_t pipeline_hash;
@@ -1872,8 +1872,7 @@ bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
gl_shader_stage stage, int idx);
struct radv_shader_variant *radv_get_shader(const struct radv_pipeline *pipeline,
gl_shader_stage stage);
struct radv_shader *radv_get_shader(const struct radv_pipeline *pipeline, gl_shader_stage stage);
struct radv_graphics_pipeline_create_info {
bool use_rectlist;

189
src/amd/vulkan/radv_shader.c
View File

@@ -1252,7 +1252,7 @@ free_shader_memory(struct radv_device *device, union radv_shader_arena_block *al
}
static void *
radv_alloc_shader_memory(struct radv_device *device, struct radv_shader_variant *shader)
radv_alloc_shader_memory(struct radv_device *device, struct radv_shader *shader)
{
shader->alloc = alloc_shader_memory(device, shader->code_size, shader);
if (!shader->alloc)
@@ -1561,17 +1561,17 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader
}
}
struct radv_shader_variant *
radv_shader_variant_create(struct radv_device *device, const struct radv_shader_binary *binary,
bool keep_shader_info, bool from_cache)
struct radv_shader *
radv_shader_create(struct radv_device *device, const struct radv_shader_binary *binary,
bool keep_shader_info, bool from_cache)
{
struct ac_shader_config config = {0};
struct ac_rtld_binary rtld_binary = {0};
struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
if (!variant)
struct radv_shader *shader = calloc(1, sizeof(struct radv_shader));
if (!shader)
return NULL;
variant->ref_count = 1;
shader->ref_count = 1;
if (binary->type == RADV_BINARY_TYPE_RTLD) {
struct ac_rtld_symbol lds_symbols[2];
@@ -1607,13 +1607,13 @@ radv_shader_variant_create(struct radv_device *device, const struct radv_shader_
};
if (!ac_rtld_open(&rtld_binary, open_info)) {
free(variant);
free(shader);
return NULL;
}
if (!ac_rtld_read_config(&device->physical_device->rad_info, &rtld_binary, &config)) {
ac_rtld_close(&rtld_binary);
free(variant);
free(shader);
return NULL;
}
@@ -1626,30 +1626,30 @@ radv_shader_variant_create(struct radv_device *device, const struct radv_shader_
config.lds_size = binary->info.tcs.num_lds_blocks;
}
variant->code_size = rtld_binary.rx_size;
variant->exec_size = rtld_binary.exec_size;
shader->code_size = rtld_binary.rx_size;
shader->exec_size = rtld_binary.exec_size;
} else {
assert(binary->type == RADV_BINARY_TYPE_LEGACY);
config = ((struct radv_shader_binary_legacy *)binary)->base.config;
variant->code_size =
shader->code_size =
radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
shader->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
}
variant->info = binary->info;
shader->info = binary->info;
if (from_cache) {
/* Copy the shader binary configuration from the cache. */
memcpy(&variant->config, &binary->config, sizeof(variant->config));
memcpy(&shader->config, &binary->config, sizeof(shader->config));
} else {
radv_postprocess_config(device, &config, &binary->info, binary->stage, &variant->config);
radv_postprocess_config(device, &config, &binary->info, binary->stage, &shader->config);
}
void *dest_ptr = radv_alloc_shader_memory(device, variant);
void *dest_ptr = radv_alloc_shader_memory(device, shader);
if (!dest_ptr) {
if (binary->type == RADV_BINARY_TYPE_RTLD)
ac_rtld_close(&rtld_binary);
free(variant);
free(shader);
return NULL;
}
@@ -1657,12 +1657,12 @@ radv_shader_variant_create(struct radv_device *device, const struct radv_shader_
struct radv_shader_binary_rtld *bin = (struct radv_shader_binary_rtld *)binary;
struct ac_rtld_upload_info info = {
.binary = &rtld_binary,
.rx_va = radv_shader_variant_get_va(variant),
.rx_va = radv_shader_get_va(shader),
.rx_ptr = dest_ptr,
};
if (!ac_rtld_upload(&info)) {
radv_shader_variant_destroy(device, variant);
radv_shader_destroy(device, shader);
ac_rtld_close(&rtld_binary);
return NULL;
}
@@ -1672,19 +1672,19 @@ radv_shader_variant_create(struct radv_device *device, const struct radv_shader_
size_t disasm_size;
if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data,
&disasm_size)) {
radv_shader_variant_destroy(device, variant);
radv_shader_destroy(device, shader);
ac_rtld_close(&rtld_binary);
return NULL;
}
variant->ir_string =
shader->ir_string =
bin->llvm_ir_size ? strdup((const char *)(bin->data + bin->elf_size)) : NULL;
variant->disasm_string = malloc(disasm_size + 1);
memcpy(variant->disasm_string, disasm_data, disasm_size);
variant->disasm_string[disasm_size] = 0;
shader->disasm_string = malloc(disasm_size + 1);
memcpy(shader->disasm_string, disasm_data, disasm_size);
shader->disasm_string[disasm_size] = 0;
}
variant->code_ptr = dest_ptr;
shader->code_ptr = dest_ptr;
ac_rtld_close(&rtld_binary);
} else {
struct radv_shader_binary_legacy *bin = (struct radv_shader_binary_legacy *)binary;
@@ -1695,20 +1695,20 @@ radv_shader_variant_create(struct radv_device *device, const struct radv_shader_
for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
variant->code_ptr = dest_ptr;
variant->ir_string =
shader->code_ptr = dest_ptr;
shader->ir_string =
bin->ir_size ? strdup((const char *)(bin->data + bin->stats_size + bin->code_size)) : NULL;
variant->disasm_string =
shader->disasm_string =
bin->disasm_size
? strdup((const char *)(bin->data + bin->stats_size + bin->code_size + bin->ir_size))
: NULL;
if (bin->stats_size) {
variant->statistics = calloc(bin->stats_size, 1);
memcpy(variant->statistics, bin->data, bin->stats_size);
shader->statistics = calloc(bin->stats_size, 1);
memcpy(shader->statistics, bin->data, bin->stats_size);
}
}
return variant;
return shader;
}
static char *
@@ -1734,12 +1734,12 @@ radv_dump_nir_shaders(struct nir_shader *const *shaders, int shader_count)
return ret;
}
static struct radv_shader_variant *
shader_variant_compile(struct radv_device *device, struct vk_shader_module *module,
struct nir_shader *const *shaders, int shader_count, gl_shader_stage stage,
struct radv_shader_info *info, struct radv_nir_compiler_options *options,
bool gs_copy_shader, bool trap_handler_shader, bool keep_shader_info,
bool keep_statistic_info, struct radv_shader_binary **binary_out)
static struct radv_shader *
shader_compile(struct radv_device *device, struct vk_shader_module *module,
struct nir_shader *const *shaders, int shader_count, gl_shader_stage stage,
struct radv_shader_info *info, struct radv_nir_compiler_options *options,
bool gs_copy_shader, bool trap_handler_shader, bool keep_shader_info,
bool keep_statistic_info, struct radv_shader_binary **binary_out)
{
enum radeon_family chip_family = device->physical_device->rad_info.family;
struct radv_shader_binary *binary = NULL;
@@ -1805,9 +1805,8 @@ shader_variant_compile(struct radv_device *device, struct vk_shader_module *modu
binary->info = *info;
struct radv_shader_variant *variant =
radv_shader_variant_create(device, binary, keep_shader_info, false);
if (!variant) {
struct radv_shader *shader = radv_shader_create(device, binary, keep_shader_info, false);
if (!shader) {
free(binary);
return NULL;
}
@@ -1817,43 +1816,43 @@ shader_variant_compile(struct radv_device *device, struct vk_shader_module *modu
for (int i = 1; i < shader_count; ++i)
fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
fprintf(stderr, "\ndisasm:\n%s\n", shader->disasm_string);
}
if (keep_shader_info) {
variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
shader->nir_string = radv_dump_nir_shaders(shaders, shader_count);
if (!gs_copy_shader && !trap_handler_shader && !module->nir) {
variant->spirv = malloc(module->size);
if (!variant->spirv) {
free(variant);
shader->spirv = malloc(module->size);
if (!shader->spirv) {
free(shader);
free(binary);
return NULL;
}
memcpy(variant->spirv, module->data, module->size);
variant->spirv_size = module->size;
memcpy(shader->spirv, module->data, module->size);
shader->spirv_size = module->size;
}
}
/* Copy the shader binary configuration to store it in the cache. */
memcpy(&binary->config, &variant->config, sizeof(binary->config));
memcpy(&binary->config, &shader->config, sizeof(binary->config));
if (binary_out)
*binary_out = binary;
else
free(binary);
return variant;
return shader;
}
struct radv_shader_variant *
radv_shader_variant_compile(struct radv_device *device, struct vk_shader_module *module,
struct nir_shader *const *shaders, int shader_count,
struct radv_pipeline_layout *layout,
const struct radv_pipeline_key *key,
struct radv_shader_info *info, bool keep_shader_info,
bool keep_statistic_info,
struct radv_shader_binary **binary_out)
struct radv_shader *
radv_shader_compile(struct radv_device *device, struct vk_shader_module *module,
struct nir_shader *const *shaders, int shader_count,
struct radv_pipeline_layout *layout,
const struct radv_pipeline_key *key,
struct radv_shader_info *info, bool keep_shader_info,
bool keep_statistic_info,
struct radv_shader_binary **binary_out)
{
gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
struct radv_nir_compiler_options options = {0};
@@ -1867,11 +1866,11 @@ radv_shader_variant_compile(struct radv_device *device, struct vk_shader_module
options.robust_buffer_access = device->robust_buffer_access;
options.wgp_mode = radv_should_use_wgp_mode(device, stage, info);
return shader_variant_compile(device, module, shaders, shader_count, stage, info, &options,
false, false, keep_shader_info, keep_statistic_info, binary_out);
return shader_compile(device, module, shaders, shader_count, stage, info, &options, false, false,
keep_shader_info, keep_statistic_info, binary_out);
}
struct radv_shader_variant *
struct radv_shader *
radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *shader,
struct radv_shader_info *info, struct radv_shader_binary **binary_out,
bool keep_shader_info, bool keep_statistic_info, bool multiview,
@@ -1885,15 +1884,15 @@ radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *shader
options.key.has_multiview_view_index = multiview;
options.key.optimisations_disabled = disable_optimizations;
return shader_variant_compile(device, NULL, &shader, 1, stage, info, &options, true, false,
keep_shader_info, keep_statistic_info, binary_out);
return shader_compile(device, NULL, &shader, 1, stage, info, &options, true, false,
keep_shader_info, keep_statistic_info, binary_out);
}
struct radv_shader_variant *
struct radv_shader *
radv_create_trap_handler_shader(struct radv_device *device)
{
struct radv_nir_compiler_options options = {0};
struct radv_shader_variant *shader = NULL;
struct radv_shader *shader = NULL;
struct radv_shader_binary *binary = NULL;
struct radv_shader_info info = {0};
@@ -1903,8 +1902,8 @@ radv_create_trap_handler_shader(struct radv_device *device)
options.wgp_mode = radv_should_use_wgp_mode(device, MESA_SHADER_COMPUTE, &info);
info.wave_size = 64;
shader = shader_variant_compile(device, NULL, &b.shader, 1, MESA_SHADER_COMPUTE, &info, &options,
false, true, true, false, &binary);
shader = shader_compile(device, NULL, &b.shader, 1, MESA_SHADER_COMPUTE, &info, &options, false,
true, true, false, &binary);
ralloc_free(b.shader);
free(binary);
@@ -1980,19 +1979,19 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke
}
void
radv_shader_variant_destroy(struct radv_device *device, struct radv_shader_variant *variant)
radv_shader_destroy(struct radv_device *device, struct radv_shader *shader)
{
if (!p_atomic_dec_zero(&variant->ref_count))
if (!p_atomic_dec_zero(&shader->ref_count))
return;
free_shader_memory(device, variant->alloc);
free_shader_memory(device, shader->alloc);
free(variant->spirv);
free(variant->nir_string);
free(variant->disasm_string);
free(variant->ir_string);
free(variant->statistics);
free(variant);
free(shader->spirv);
free(shader->nir_string);
free(shader->disasm_string);
free(shader->ir_string);
free(shader->statistics);
free(shader);
}
void
@@ -2006,13 +2005,13 @@ radv_prolog_destroy(struct radv_device *device, struct radv_shader_prolog *prolo
}
uint64_t
radv_shader_variant_get_va(const struct radv_shader_variant *variant)
radv_shader_get_va(const struct radv_shader *shader)
{
return radv_buffer_get_va(variant->bo) + variant->alloc->offset;
return radv_buffer_get_va(shader->bo) + shader->alloc->offset;
}
struct radv_shader_variant *
radv_find_shader_variant(struct radv_device *device, uint64_t pc)
struct radv_shader *
radv_find_shader(struct radv_device *device, uint64_t pc)
{
mtx_lock(&device->shader_arena_mutex);
list_for_each_entry(struct radv_shader_arena, arena, &device->shader_arenas, list)
@@ -2029,7 +2028,7 @@ radv_find_shader_variant(struct radv_device *device, uint64_t pc)
uint64_t start = radv_buffer_get_va(block->arena->bo) + block->offset;
if (!block->freelist.prev && pc >= start && pc < start + block->size) {
mtx_unlock(&device->shader_arena_mutex);
return (struct radv_shader_variant *)block->freelist.next;
return (struct radv_shader *)block->freelist.next;
}
}
}
@@ -2072,13 +2071,13 @@ radv_get_shader_name(struct radv_shader_info *info, gl_shader_stage stage)
}
unsigned
radv_get_max_waves(const struct radv_device *device, struct radv_shader_variant *variant,
radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader,
gl_shader_stage stage)
{
struct radeon_info *info = &device->physical_device->rad_info;
enum chip_class chip_class = info->chip_class;
uint8_t wave_size = variant->info.wave_size;
struct ac_shader_config *conf = &variant->config;
uint8_t wave_size = shader->info.wave_size;
struct ac_shader_config *conf = &shader->config;
unsigned max_simd_waves;
unsigned lds_per_wave = 0;
@@ -2086,10 +2085,10 @@ radv_get_max_waves(const struct radv_device *device, struct radv_shader_variant
if (stage == MESA_SHADER_FRAGMENT) {
lds_per_wave =
conf->lds_size * info->lds_encode_granularity + variant->info.ps.num_interp * 48;
conf->lds_size * info->lds_encode_granularity + shader->info.ps.num_interp * 48;
lds_per_wave = align(lds_per_wave, info->lds_alloc_granularity);
} else if (stage == MESA_SHADER_COMPUTE) {
unsigned max_workgroup_size = variant->info.workgroup_size;
unsigned max_workgroup_size = shader->info.workgroup_size;
lds_per_wave =
align(conf->lds_size * info->lds_encode_granularity, info->lds_alloc_granularity);
lds_per_wave /= DIV_ROUND_UP(max_workgroup_size, wave_size);
@@ -2176,12 +2175,12 @@ radv_GetShaderInfoAMD(VkDevice _device, VkPipeline _pipeline, VkShaderStageFlagB
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
struct radv_shader_variant *variant = pipeline->shaders[stage];
struct radv_shader *shader = pipeline->shaders[stage];
VkResult result = VK_SUCCESS;
/* Spec doesn't indicate what to do if the stage is invalid, so just
* return no info for this. */
if (!variant)
if (!shader)
return vk_error(device, VK_ERROR_FEATURE_NOT_PRESENT);
switch (infoType) {
@@ -2190,7 +2189,7 @@ radv_GetShaderInfoAMD(VkDevice _device, VkPipeline _pipeline, VkShaderStageFlagB
*pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
} else {
unsigned lds_multiplier = device->physical_device->rad_info.lds_encode_granularity;
struct ac_shader_config *conf = &variant->config;
struct ac_shader_config *conf = &shader->config;
VkShaderStatisticsInfoAMD statistics = {0};
statistics.shaderStageMask = shaderStage;
@@ -2201,7 +2200,7 @@ radv_GetShaderInfoAMD(VkDevice _device, VkPipeline _pipeline, VkShaderStageFlagB
statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
if (stage == MESA_SHADER_COMPUTE) {
unsigned *local_size = variant->info.cs.block_size;
unsigned *local_size = shader->info.cs.block_size;
unsigned workgroup_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.workgroup_size;
statistics.numAvailableVgprs =
@@ -2238,10 +2237,10 @@ radv_GetShaderInfoAMD(VkDevice _device, VkPipeline _pipeline, VkShaderStageFlagB
u_memstream_open(&mem, &out, &outsize);
FILE *const memf = u_memstream_get(&mem);
fprintf(memf, "%s:\n", radv_get_shader_name(&variant->info, stage));
fprintf(memf, "%s\n\n", variant->ir_string);
if (variant->disasm_string) {
fprintf(memf, "%s\n\n", variant->disasm_string);
fprintf(memf, "%s:\n", radv_get_shader_name(&shader->info, stage));
fprintf(memf, "%s\n\n", shader->ir_string);
if (shader->disasm_string) {
fprintf(memf, "%s\n\n", shader->disasm_string);
}
radv_dump_shader_stats(device, pipeline, stage, memf);
u_memstream_close(&mem);
@@ -2277,7 +2276,7 @@ VkResult
radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline *pipeline,
gl_shader_stage stage, FILE *output)
{
struct radv_shader_variant *shader = pipeline->shaders[stage];
struct radv_shader *shader = pipeline->shaders[stage];
VkPipelineExecutablePropertiesKHR *props = NULL;
uint32_t prop_count = 0;
VkResult result;

22
src/amd/vulkan/radv_shader.h
View File

@@ -454,7 +454,7 @@ union radv_shader_arena_block {
};
};
struct radv_shader_variant {
struct radv_shader {
uint32_t ref_count;
struct radeon_winsys_bo *bo;
@@ -505,34 +505,34 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
VkPipelineCreationFeedbackEXT *pipeline_feedback,
VkPipelineCreationFeedbackEXT **stage_feedbacks);
struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
const struct radv_shader_binary *binary,
bool keep_shader_info, bool from_cache);
struct radv_shader_variant *radv_shader_variant_compile(
struct radv_shader *radv_shader_create(struct radv_device *device,
const struct radv_shader_binary *binary,
bool keep_shader_info, bool from_cache);
struct radv_shader *radv_shader_compile(
struct radv_device *device, struct vk_shader_module *module, struct nir_shader *const *shaders,
int shader_count, struct radv_pipeline_layout *layout, const struct radv_pipeline_key *key,
struct radv_shader_info *info, bool keep_shader_info, bool keep_statistic_info,
struct radv_shader_binary **binary_out);
struct radv_shader_variant *
struct radv_shader *
radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
struct radv_shader_info *info, struct radv_shader_binary **binary_out,
bool multiview, bool keep_shader_info, bool keep_statistic_info,
bool disable_optimizations);
struct radv_shader_variant *radv_create_trap_handler_shader(struct radv_device *device);
struct radv_shader *radv_create_trap_handler_shader(struct radv_device *device);
struct radv_shader_prolog *radv_create_vs_prolog(struct radv_device *device,
const struct radv_vs_prolog_key *key);
void radv_shader_variant_destroy(struct radv_device *device, struct radv_shader_variant *variant);
void radv_shader_destroy(struct radv_device *device, struct radv_shader *shader);
void radv_prolog_destroy(struct radv_device *device, struct radv_shader_prolog *prolog);
uint64_t radv_shader_variant_get_va(const struct radv_shader_variant *variant);
struct radv_shader_variant *radv_find_shader_variant(struct radv_device *device, uint64_t pc);
uint64_t radv_shader_get_va(const struct radv_shader *shader);
struct radv_shader *radv_find_shader(struct radv_device *device, uint64_t pc);
unsigned radv_get_max_waves(const struct radv_device *device, struct radv_shader_variant *variant,
unsigned radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader,
gl_shader_stage stage);
const char *radv_get_shader_name(struct radv_shader_info *info, gl_shader_stage stage);

4
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -139,7 +139,7 @@ si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs)
assert(device->physical_device->rad_info.chip_class == GFX8);
tba_va = radv_shader_variant_get_va(device->trap_handler_shader);
tba_va = radv_shader_get_va(device->trap_handler_shader);
tma_va = radv_buffer_get_va(device->tma_bo);
radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4);
@@ -531,7 +531,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
assert(device->physical_device->rad_info.chip_class == GFX8);
tba_va = radv_shader_variant_get_va(device->trap_handler_shader);
tba_va = radv_shader_get_va(device->trap_handler_shader);
tma_va = radv_buffer_get_va(device->tma_bo);
uint32_t regs[] = {R_00B000_SPI_SHADER_TBA_LO_PS, R_00B100_SPI_SHADER_TBA_LO_VS,