diff --git a/src/nouveau/compiler/nak/api.rs b/src/nouveau/compiler/nak/api.rs
index 62b7e482400..317a53eaf2c 100644
--- a/src/nouveau/compiler/nak/api.rs
+++ b/src/nouveau/compiler/nak/api.rs
@@ -136,6 +136,7 @@ fn nir_options(dev: &nv_device_info) -> nir_shader_compiler_options {
     // We set .ftz on f32 by default so we can support fmulz whenever the client
     // doesn't explicitly request denorms.
     op.has_fmulz_no_denorms = true;
+    op.has_find_msb_rev = true;
     op.has_pack_half_2x16_rtz = true;
 
     op.max_unroll_iterations = 32;
diff --git a/src/nouveau/compiler/nak/from_nir.rs b/src/nouveau/compiler/nak/from_nir.rs
index fed75ad1a35..d15b2447c93 100644
--- a/src/nouveau/compiler/nak/from_nir.rs
+++ b/src/nouveau/compiler/nak/from_nir.rs
@@ -1015,13 +1015,22 @@ impl<'a> ShaderFromNir<'a> {
                     b.isetp(IntCmpType::I32, IntCmpOp::Eq, srcs[0], srcs[1])
                 }
             }
-            nir_op_ifind_msb | nir_op_ufind_msb => {
+            nir_op_ifind_msb | nir_op_ifind_msb_rev | nir_op_ufind_msb
+            | nir_op_ufind_msb_rev => {
                 let dst = b.alloc_ssa(RegFile::GPR, 1);
                 b.push_op(OpFlo {
                     dst: dst.into(),
                     src: srcs[0],
-                    signed: alu.op == nir_op_ifind_msb,
-                    return_shift_amount: false,
+                    signed: match alu.op {
+                        nir_op_ifind_msb | nir_op_ifind_msb_rev => true,
+                        nir_op_ufind_msb | nir_op_ufind_msb_rev => false,
+                        _ => panic!("Not a find_msb op"),
+                    },
+                    return_shift_amount: match alu.op {
+                        nir_op_ifind_msb | nir_op_ufind_msb => false,
+                        nir_op_ifind_msb_rev | nir_op_ufind_msb_rev => true,
+                        _ => panic!("Not a find_msb op"),
+                    },
                 });
                 dst
             }