intel/perf: Do not add INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_PEC
MI_REPORT_PERF_COUNT reports all 64 PEC counters, so there is no need to read individual registers. Also the individual registers reads privileged and UMDs can't access it, causing it to always read as always zero and overwritting valid data read with MI_REPORT_PERF_COUNT. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29529>
This commit is contained in:

committed by
Marge Bot

parent
7b5bf6dcca
commit
9b5ba06122
@@ -1505,11 +1505,6 @@ intel_perf_init_query_fields(struct intel_perf_config *perf_cfg,
|
||||
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
|
||||
GFX12_OAG_PERF_C32(i), 4, i);
|
||||
}
|
||||
} else if (devinfo->verx10 >= 200) {
|
||||
for (uint32_t i = 0; i < XE2_N_OAG_PERF_PEC; i++) {
|
||||
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_PEC,
|
||||
XE2_OAG_PERF_PEC(i), 8, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@@ -74,9 +74,6 @@
|
||||
#define GFX125_OAG_PERF_A36 (0xdb20)
|
||||
#define GFX125_OAG_PERF_A37 (0xdb28)
|
||||
|
||||
#define XE2_N_OAG_PERF_PEC 64
|
||||
#define XE2_OAG_PERF_PEC(idx) (0x14200 + (idx) * 8)
|
||||
|
||||
/* Pipeline statistic counters */
|
||||
#define IA_VERTICES_COUNT 0x2310
|
||||
#define IA_PRIMITIVES_COUNT 0x2318
|
||||
|
Reference in New Issue
Block a user