radeonsi: adjust tess SGPRs to allow fully occupied 3 HS waves of triangles
With triangles and 3 HS waves, 3 lanes were unoccupied. Adjust the SGPR encoding to allow 1 more triangle to fit there. Some of the fields are not large enough, but they weren't large enough before either. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7623>
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@@ -117,25 +117,25 @@ struct si_shader_context {
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/* API TCS & TES */
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/* Layout of TCS outputs in the offchip buffer
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* # 6 bits
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* [0:5] = the number of patches per threadgroup, max = NUM_PATCHES (40)
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* # 6 bits
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* [6:11] = the number of output vertices per patch, max = 32
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* # 20 bits
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* [12:31] = the offset of per patch attributes in the buffer in bytes.
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* max = NUM_PATCHES*32*32*16
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* [0:5] = the number of patches per threadgroup - 1, max = 63
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* # 5 bits
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* [6:10] = the number of output vertices per patch - 1, max = 31
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* # 21 bits
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* [11:31] = the offset of per patch attributes in the buffer in bytes.
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* max = NUM_PATCHES*32*32*16 = 1M
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*/
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struct ac_arg tcs_offchip_layout;
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/* API TCS */
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/* Offsets where TCS outputs and TCS patch outputs live in LDS:
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* [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
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* [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32 = 64K (TODO: not enough bits)
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* [16:31] = TCS output patch0 offset for per-patch / 16
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* max = (NUM_PATCHES + 1) * 32*32
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* max = (NUM_PATCHES + 1) * 32*32 = 66624 (TODO: not enough bits)
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*/
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struct ac_arg tcs_out_lds_offsets;
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/* Layout of TCS outputs / TES inputs:
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* [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
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* max = 32*32*4 + 32*4
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* max = 32*32*4 + 32*4 = 4224
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* [13:18] = gl_PatchVerticesIn, max = 32
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* [19:31] = high 13 bits of the 32-bit address of tessellation ring buffers
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*/
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