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radv: fix 16-bit support in radv_lower_vs_input

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: b366fef091 ("radv: optimize the number of loaded components for VS inputs in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
This commit is contained in:
Rhys Perry
2022-08-04 17:54:56 +01:00
committed by Marge Bot
parent 82f9e40851
commit 9ae13a9bd3
1 changed files with 3 additions and 2 deletions
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5
src/amd/vulkan/radv_pipeline.c
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@@ -3864,9 +3864,10 @@ radv_lower_vs_input(nir_shader *nir, const struct radv_pipeline_key *pipeline_ke
if (swizzle[i + component] < num_channels) {
channels[i] = nir_channel(&b, &intrin->dest.ssa, swizzle[idx]);
} else if (i + component == 3) {
channels[i] = is_float ? nir_imm_float(&b, 1.0f) : nir_imm_int(&b, 1u);
channels[i] = is_float ? nir_imm_floatN_t(&b, 1.0f, intrin->dest.ssa.bit_size)
: nir_imm_intN_t(&b, 1u, intrin->dest.ssa.bit_size);
} else {
channels[i] = nir_imm_zero(&b, 1, 32);
channels[i] = nir_imm_zero(&b, 1, intrin->dest.ssa.bit_size);
}
}