From 9ae13a9bd39e6b71ae0748d1cca598dce13f6306 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Thu, 4 Aug 2022 17:54:56 +0100 Subject: [PATCH] radv: fix 16-bit support in radv_lower_vs_input Signed-off-by: Rhys Perry Reviewed-by: Samuel Pitoiset Fixes: b366fef091d ("radv: optimize the number of loaded components for VS inputs in NIR") Part-of: --- src/amd/vulkan/radv_pipeline.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 13fd8da20f7..1d77be9b338 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3864,9 +3864,10 @@ radv_lower_vs_input(nir_shader *nir, const struct radv_pipeline_key *pipeline_ke if (swizzle[i + component] < num_channels) { channels[i] = nir_channel(&b, &intrin->dest.ssa, swizzle[idx]); } else if (i + component == 3) { - channels[i] = is_float ? nir_imm_float(&b, 1.0f) : nir_imm_int(&b, 1u); + channels[i] = is_float ? nir_imm_floatN_t(&b, 1.0f, intrin->dest.ssa.bit_size) + : nir_imm_intN_t(&b, 1u, intrin->dest.ssa.bit_size); } else { - channels[i] = nir_imm_zero(&b, 1, 32); + channels[i] = nir_imm_zero(&b, 1, intrin->dest.ssa.bit_size); } }