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intel/compiler: implement primitive shading rate for mesh

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16030>
This commit is contained in:
Marcin Ślusarz
2022-04-12 15:06:16 +02:00
committed by Marge Bot
parent f575b0d7b5
commit 9acb30c8c4
3 changed files with 30 additions and 15 deletions
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16
src/intel/compiler/brw_fs.cpp
View File

@@ -1799,16 +1799,22 @@ calculate_urb_setup(const struct intel_device_info *devinfo,
uint64_t per_prim_inputs_read = uint64_t per_prim_inputs_read =
nir->info.inputs_read & nir->info.per_primitive_inputs; nir->info.inputs_read & nir->info.per_primitive_inputs;
/* In Mesh, VIEWPORT and LAYER slots are always at the beginning, /* In Mesh, PRIMITIVE_SHADING_RATE, VIEWPORT and LAYER slots
* because they come from MUE Primitive Header, not Per-Primitive Attributes. * are always at the beginning, because they come from MUE
* Primitive Header, not Per-Primitive Attributes.
*/ */
const uint64_t primitive_header_bits = VARYING_BIT_VIEWPORT | const uint64_t primitive_header_bits = VARYING_BIT_VIEWPORT |
VARYING_BIT_LAYER; VARYING_BIT_LAYER |
VARYING_BIT_PRIMITIVE_SHADING_RATE;
if (per_prim_inputs_read & primitive_header_bits) { if (per_prim_inputs_read & primitive_header_bits) {
/* Layer and Viewport live in the same 4-dwords slot (layer /* Primitive Shading Rate, Layer and Viewport live in the same
* is dword 1, and viewport is dword 2). * 4-dwords slot (psr is dword 0, layer is dword 1, and viewport
* is dword 2).
*/ */
if (per_prim_inputs_read & VARYING_BIT_PRIMITIVE_SHADING_RATE)
prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_SHADING_RATE] = 0;
if (per_prim_inputs_read & VARYING_BIT_LAYER) if (per_prim_inputs_read & VARYING_BIT_LAYER)
prog_data->urb_setup[VARYING_SLOT_LAYER] = 0; prog_data->urb_setup[VARYING_SLOT_LAYER] = 0;

6
src/intel/compiler/brw_mesh.cpp
View File

@@ -362,6 +362,7 @@ brw_compute_mue_map(struct nir_shader *nir, struct brw_mue_map *map)
map->per_primitive_header_size_dw = map->per_primitive_header_size_dw =
(nir->info.outputs_written & (BITFIELD64_BIT(VARYING_SLOT_VIEWPORT) | (nir->info.outputs_written & (BITFIELD64_BIT(VARYING_SLOT_VIEWPORT) |
BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE) | BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE) |
BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE) |
BITFIELD64_BIT(VARYING_SLOT_LAYER))) ? 8 : 0; BITFIELD64_BIT(VARYING_SLOT_LAYER))) ? 8 : 0;
map->per_primitive_start_dw = ALIGN(primitive_list_size_dw, 8); map->per_primitive_start_dw = ALIGN(primitive_list_size_dw, 8);
@@ -372,6 +373,9 @@ brw_compute_mue_map(struct nir_shader *nir, struct brw_mue_map *map)
unsigned start; unsigned start;
switch (location) { switch (location) {
case VARYING_SLOT_PRIMITIVE_SHADING_RATE:
start = map->per_primitive_start_dw + 0;
break;
case VARYING_SLOT_LAYER: case VARYING_SLOT_LAYER:
start = map->per_primitive_start_dw + 1; /* RTAIndex */ start = map->per_primitive_start_dw + 1; /* RTAIndex */
break; break;
@@ -508,6 +512,8 @@ brw_nir_lower_mue_outputs(nir_shader *nir, const struct brw_mue_map *map)
nir_lower_io(nir, nir_var_shader_out, type_size_scalar_dwords, nir_lower_io(nir, nir_var_shader_out, type_size_scalar_dwords,
nir_lower_io_lower_64bit_to_32); nir_lower_io_lower_64bit_to_32);
brw_nir_lower_shading_rate_output(nir);
} }
static void static void

23
src/intel/compiler/brw_nir_lower_shading_rate_output.c
View File

@@ -54,17 +54,24 @@ lower_shading_rate_output_instr(nir_builder *b, nir_instr *instr,
return false; return false;
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
if (intrin->intrinsic != nir_intrinsic_load_output && nir_intrinsic_op op = intrin->intrinsic;
intrin->intrinsic != nir_intrinsic_store_output)
if (op != nir_intrinsic_load_output &&
op != nir_intrinsic_store_output &&
op != nir_intrinsic_load_per_primitive_output &&
op != nir_intrinsic_store_per_primitive_output)
return false; return false;
if (nir_intrinsic_base(intrin) != VARYING_SLOT_PRIMITIVE_SHADING_RATE) struct nir_io_semantics io = nir_intrinsic_io_semantics(intrin);
if (io.location != VARYING_SLOT_PRIMITIVE_SHADING_RATE)
return false; return false;
b->cursor = intrin->intrinsic == nir_intrinsic_load_output ? bool is_store = op == nir_intrinsic_store_output ||
nir_after_instr(instr) : nir_before_instr(instr); op == nir_intrinsic_store_per_primitive_output;
if (intrin->intrinsic == nir_intrinsic_store_output) { b->cursor = is_store ? nir_before_instr(instr) : nir_after_instr(instr);
if (is_store) {
assert(intrin->src[0].is_ssa); assert(intrin->src[0].is_ssa);
nir_ssa_def *bit_field = intrin->src[0].ssa; nir_ssa_def *bit_field = intrin->src[0].ssa;
nir_ssa_def *fp16_x = nir_ssa_def *fp16_x =
@@ -80,7 +87,6 @@ lower_shading_rate_output_instr(nir_builder *b, nir_instr *instr,
nir_instr_rewrite_src(instr, &intrin->src[0], nir_instr_rewrite_src(instr, &intrin->src[0],
nir_src_for_ssa(packed_fp16_xy)); nir_src_for_ssa(packed_fp16_xy));
} else { } else {
assert(intrin->intrinsic == nir_intrinsic_load_output);
nir_ssa_def *packed_fp16_xy = &intrin->dest.ssa; nir_ssa_def *packed_fp16_xy = &intrin->dest.ssa;
nir_ssa_def *u32_x = nir_ssa_def *u32_x =
@@ -102,9 +108,6 @@ lower_shading_rate_output_instr(nir_builder *b, nir_instr *instr,
bool bool
brw_nir_lower_shading_rate_output(nir_shader *nir) brw_nir_lower_shading_rate_output(nir_shader *nir)
{ {
/* TODO(mesh): Add Shading Rate support. */
assert(nir->info.stage != MESA_SHADER_MESH);
return nir_shader_instructions_pass(nir, lower_shading_rate_output_instr, return nir_shader_instructions_pass(nir, lower_shading_rate_output_instr,
nir_metadata_block_index | nir_metadata_block_index |
nir_metadata_dominance, NULL); nir_metadata_dominance, NULL);